[Bug rtl-optimization/44141] Redundant loads and stores generated for AMD bdver1 target

["jakub at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44141

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |jakub at gcc dot gnu.org

--- Comment #12 from Jakub Jelinek <jakub at gcc dot gnu.org> 2012-03-28 07:47:58 UTC ---
Having a vector mode changing subreg on the LHS of an instruction is a very
common issue in the i386 backend, and unfortunately e.g. means that lots of
insns can't be combined or simplified.  I wonder if the expansion sometimes
shouldn't use a non-subregged temporary as lhs and add a move from subreg of
the temporary to the desired destination.

BTW, if with TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL ps is more desirable than pd
for movs, then perhaps it would be better to add a mode attr similar to
ssemodesuffix, which would emit pd or ps for V2DFmode depending on
TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL (see e.g. i128 mode attr).