[Bug rtl-optimization/51821] [4.5/4.6/4.7 Regression] 64bit > 32bit conversion produces incorrect results with optimizations

["ebotcazou at gcc dot gnu.org" <gcc-bugzilla at gcc dot gnu dot org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=51821

--- Comment #12 from Eric Botcazou <ebotcazou at gcc dot gnu.org> 2012-01-12 11:18:37 UTC ---
> I think that DF is OK, the problem is in recog.c/peep2_find_free_register, with
> this loop:
> 
>   while (from != to)
>     {
>       HARD_REG_SET this_live;
> 
>       from = peep2_buf_position (from + 1);
>       gcc_assert (peep2_insn_data[from].insn != NULL_RTX);
>       REG_SET_TO_HARD_REG_SET (this_live, peep2_insn_data[from].live_before);
>       IOR_HARD_REG_SET (live, this_live);
>     }
> 
> Here we need to analyse the insn patterns for ALL sets and clobbers, not only
> track live registers through the insn stream.

I'm not sure I understand.  If the peephole matches, then the insn pattern is
present in the insn stream with instantiated registers, so it's sufficient to
scan the insn stream.  AFAICS the code doesn't see that edx is live after the
instruction because DF reports that only eax is; of course it's eax in DImode
so edx is "implicitly" live, but it's nevertheless live.