Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3f0cdc6c53e82fda41555e3a084d20d11a575076..19f595b306641c796c6127e825b1a058ea8f1efe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2021-03-22  Kito Cheng  <kito.cheng@sifive.com>
+
+       Backported from master:
+       2021-03-22  Kito Cheng  <kito.cheng@sifive.com>
+
+       PR target/99702
+       * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
+       after type checking.
+
 2021-03-18  Sinan Lin  <sinan@isrc.iscas.ac.cn>
 
        Backported from master:

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e5e2f23c9ec595be2d660264cbf725290daef0aa..c3b41601deecef6f20a7bb10492db3df7fd0037d 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20210322
+20210323

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index b4e8a21d4f2eb5bc2767e6bb618641f120e72bfb..6c17669b12763df3063c3dbb5fd252741a6f7de4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2021-03-22  Kito Cheng  <kito.cheng@sifive.com>
+
+       Backported from master:
+       2021-03-22  Kito Cheng  <kito.cheng@sifive.com>
+
+       PR target/99702
+       * gcc.target/riscv/pr99702.c: New.
+
 2021-03-20  Harald Anlauf  <anlauf@gmx.de>
 
        Backported from master: