The table below shows various characteristics for all architectures supported by GCC. It can be used to determine an appropriate variety of targets on which to test patches, and is also used by GCC maintainers to track criteria that are considered when determining which targets to obsolete.
Each characteristic has a unique letter. Characteristics describing fundamental properties of the architecture or target use uppercase letters, and characteristics describing properties of the GCC port to that architecture use lowercase letters. The appearance of a letter means that the architecture has that characteristic, a blank means it does not, and a question mark means the author didn't know whether the architecture had the characteristic or not. For criteria used to determine whether an architecture should be obsoleted, the appearance of a letter is the less common case and the lack of a letter is the common case.
Architectures are identified by the names of their subdirectories in gcc/config, not by the CPU fields that config.guess reports.
Architecture characteristic key ----------------------------------------------------------------------- H A hardware implementation does not exist. M A hardware implementation is not currently being manufactured. S A Free simulator does not exist. L Integer registers are narrower than 32 bits. Q Integer registers are at least 64 bits wide. N Memory is not byte addressable, and/or bytes are not eight bits. F Floating point arithmetic is not included in the instruction set I Architecture does not use IEEE format floating point numbers C Architecture does not have a single condition code register. B Architecture has delay slots. D Architecture has a stack that grows upward. l Port cannot use ILP32 mode integer arithmetic. q Port can use LP64 mode integer arithmetic. r Port can switch between ILP32 and LP64 at runtime. (Not necessarily supported by all subtargets.) c Port uses cc0. p Port uses define_peephole (as opposed to define_peephole2). b Port uses '"* ..."' notation for output template code. f Port does not define prologue and/or epilogue RTL expanders. m Port does not use define_constants. g Port does not define TARGET_ASM_FUNCTION_(PRO|EPI)LOGUE. i Port generates multiple inheritance thunks using TARGET_ASM_OUTPUT_MI(_VCALL)_THUNK. a Port uses LRA (by default, i.e. unless overridden by a switch). t All insns either produce exactly one assembly instruction, or trigger a define_split. e <arch>-elf is not a supported target. s <arch>-elf is the correct target to use with the simulator in /cvs/src.
| Characteristics Target | HMSLQNFICBD lqrcpbfmgiates -----------+--------------------------- aarch64 | Q q b gia s alpha | ?? Q C q mgi e arc | B b gia arm | b ia s avr | L FI l cp g bfin | F gi c6x | S CB gi cr16 | L F C g s cris | F B c gi s csky | b ia epiphany | C gi s fr30 | ?? FI B pb mg s frv | ?? B b i s gcn | S C D q a e h8300 | FI B c g s i386 | ? Q q b ia ia64 | ? Q C qr b m i iq2000 | ??? FICB b g t lm32 | F g m32c | L FI l b g s m32r | FI b s m68k | ? cpb i mcore | ? FI pb mg s mep | F C b g t s microblaze | CB i s mips | Q CB qr ia s mmix | HM Q C q i e mn10300 | ?? c gi s moxie | F g t s msp430 | L FI l b g s nds32 | F C ia s nios2 | C ia nvptx | S Q C q mg e pa | ? Q CBD qr b i e pdp11 | L IC qr b e powerpcspe | Q C qr pb ia riscv | Q C qr gia rl78 | L F l g s rs6000 | Q C qr pb ia rx | s s390 | ? Q qr gia e sh | Q CB qr p i sparc | Q CB qr b ia spu | ? Q *C mgi stormy16 | ???L FIC D l b i tilegx | S Q C q gi e tilepro | S F C gi e v850 | g a s vax | M? I c b i e visium | B g t s xtensa | C
For AVR simulator, see https://gcc.gnu.org/ml/gcc/2003-10/msg00027.html.
For ARC simulator, see https://github.com/foss-for-synopsys-dwc-arc-processors/binutils-gdb.
* SPU's float is special; it has the same format as IEEE float but has an extended range and no infinity or NaNs. SPU's float will not produce denormal or negative zeros; both are treated as positive zero. On the other hand, SPU's double is IEEE floating point.
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