Re: [patch 1/3] AMD bdver2 processors - BMI

[Quentin Neill <quentin dot neill dot gnu at gmail dot com>]

On Mon, Oct 18, 2010 at 6:19 PM, Richard Henderson <rth@redhat.com> wrote:
> On 10/18/2010 04:01 PM, Quentin Neill wrote:
>> You might have access to the full TBM/BMI spec via our NDA website:
>> https://nda.amd.com/dds/user/doc/12810D23584.PDF
>
> I do not, as far as I know. ?I'll ask around to see if someone
> has a login there.
>
> On a related note, can you tell me if "43479 3.04 November 2009"
> is the most recent version of the XOP spec?
>
> While attempting to adjust the FMA4 patterns to support the generic
> FMA support that was added this week, I noticed that the scalar
> versions of the FMA patterns (1) do not match the comments and in
> fact generate invalid rtl and (2) the comments do not match the
> above XOP spec.
>
> In particular, the comment follows the "addss" method and says
> that the upper bits are unmodified, whereas the above spec says
> that the upper bits are zeroed.
>
>
> r~
>
On Mon, Oct 18, 2010 at 2:25 PM, Richard Henderson <rth@redhat.com> wrote:
> On 10/15/2010 11:45 AM, Quentin Neill wrote:
>> The public specifications for BMI and TBM are in progress (they are
>> today available under NDA).  They will appear in one of the AMD64
>> Architecture Programmer's Manual Volumes 3-6.   I can post the
>> mnemonics definitions if needed.
>
> Please do.  From the names, it *seems* like most of the BMI insns
> should be represented with normal RTL and not via unspecs.  Which
> also begs the question of why there would need to be builtins for
> some of them.
>
> r~


Mnemonics/short description for TBM instructions below
--
Quentin

# TBM Instructions

#BEXTR dest, src, cntl - Bit Field Extract (imm): extract src[S+L-1:S]
to dest, where L=cntl[15:8] and S=cntl[7:0]
BEXTR reg32, reg/mem32, imm32 8F RXB.0A 0.1111.0.00 10 /r /id
BEXTR reg64, reg/mem64, imm32 8F RXB.0A 1.1111.0.00 10 /r /id

#BLCFILL dest, src - Fill from Lowest Clear Bit (X&(X+1)): clear
dest[L:0], where L is LSB in src
BLCFILL reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /1
BLCFILL reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /1

#BLCI dest, src - Isolate Lowest Clear Bit (X|~(X+1)): set all bits in
dest, except LS zero bit from src
BLCI reg32, reg/mem32 8F RXB.09 0.dest.0.00 02 /6
BLCI reg64, reg/mem64 8F RXB.09 1.dest.0.00 02 /6

#BLCIC dest, src - Isolate Lowest Clear Bit and Complement (~X&(X+1)):
set dest[L] to one, where L is LS zero bit from src
BLCIC reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /5
BLCIC reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /5

#BLCMSK dest, src - Mask From Lowest Clear Bit (X^(X+1)): set
dest[L:0] to one, where L is LS zero bit from src
BLCMSK reg32, reg/mem32 8F RXB.09 0.dest.0.00 02 /1
BLCMSK reg64, reg/mem64 8F RXB.09 1.dest.0.00 02 /1

#BLCS dest, src - Set Lowest Clear Bit (X|(X+1)): copy src to dest and
set dest[L] bit, where L is LS zero bit from src
BLCS reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /3
BLCS reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /3

#BLSFILL dest, src - Fill From Lowest Set Bit (X|(X-1)): set dest[L:0]
to one, where L is LSB from src
BLSFILL reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /2
BLSFILL reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /2

#BLSIC dest, src - Isolate Lowest Set Bit and Complement (~X|(X-1)):
set all bits and clear dest[L], where L is LSB from src
BLSIC reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /6
BLSIC reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /6

#T1MSKC dest, src - Inverse Mask from Trailing Ones (~X|(X+1)): set
dest[:L] to one (including L), where L is LS zero from src
T1MSKC reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /7
T1MSKC reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /7

#TZMSK dest, src - Mask From Trailing Zeros (~X&(X+1)): clear
dest[L:0] (including L), where L is LSB from src
TZMSK reg32, reg/mem32 8F RXB.09 0.dest.0.00 01 /4
TZMSK reg64, reg/mem64 8F RXB.09 1.dest.0.00 01 /4