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[RFC PATCH, i386]: PR 36793: x86-64 does not get __sync_synchronize right
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 22 Nov 2008 19:26:10 +0100
- Subject: [RFC PATCH, i386]: PR 36793: x86-64 does not get __sync_synchronize right
Hello!
This patch just wires "memory_barrier" named pattern to mfence insn.
2008-11-22 Uros Bizjak <ubizjak@gmail.com>
PR target/36793
* config/i386/sync.md (memory_barrier): New expander.
Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.
I will wait a day or two before for possible comments on this patch.
BTW: "lock nop" as suggested in PR for !TARGET_SSE2 case generates
invalid insn exception.
Thanks,
Uros.
Index: sync.md
===================================================================
--- sync.md (revision 142123)
+++ sync.md (working copy)
@@ -31,6 +31,15 @@
(define_mode_attr doublemodesuffix [(DI "8") (TI "16")])
(define_mode_attr DCASHMODE [(DI "SI") (TI "DI")])
+(define_expand "memory_barrier"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
+ "TARGET_SSE2"
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+})
+
;; ??? It would be possible to use cmpxchg8b on pentium for DImode
;; changes. It's complicated because the insn uses ecx:ebx as the
;; new value; note that the registers are reversed from the order