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[PATCH, i386]: Fix PR target/36992

Hello!

Attached patch fixes PR target/36992 by adding a SSE reg-reg alternative to vec_concatv2di insn patterns, following updated documentation from Intel. "movq xmm, xmm" insn fills upper 64bit with zeroes also for reg-reg moves.

The testcase from PR also exposes wrong register allocation choice for -O0. DImode value is passed through MMX register for 64bit targets, and we want to avoid this due to mmx-x87 register file switching problems. This problem is fixed by penalizing SSE register allocation to avoid SSE->MMX conversions.

The patch was bootstrapped and regression tested on x86_64 {,-m32}.

2008-08-02 Uros Bizjak <ubizjak@gmail.com>

   PR target/36992
   * config/i386/sse.md (vec_concatv2di): Add Y2 constraint to
   alternative 0 of operand 1.
   (*vec_concatv2di_rex64_sse): Ditto.
   (*vec_concatv2di_rex64_sse4_1): Add x constraint to alternative 0
   of operand 1.
   (*sse2_storeq_rex64): Penalize allocation of "r" registers.
   * config/i386/mmx.md (*mov<mode>_internal_rex64): Penalize allocation
   of "Y2" registers to avoid SSE <-> MMX conversions for DImode moves.
   (*movv2sf_internal_rex64): Ditto.

testsuite/ChangeLog:

2008-08-02 Uros Bizjak <ubizjak@gmail.com>

   PR target/36992
   * gcc.target/i386/pr36992-1.c: New test.
   * gcc.target/i386/pr36992-2.c: Ditto.

Uros. 
Index: config/i386/mmx.md
===================================================================
--- config/i386/mmx.md	(revision 138553)
+++ config/i386/mmx.md	(working copy)
@@ -65,9 +65,9 @@
 
 (define_insn "*mov<mode>_internal_rex64"
   [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
-				"=rm,r,!?y,!?y ,m  ,!y,Y2,x,x ,m,r,x")
+				"=rm,r,!?y,!?y ,m  ,!y,*Y2,x,x ,m,r,x")
 	(match_operand:MMXMODEI8 1 "vector_move_operand"
-				"Cr ,m,C  ,!?ym,!?y,Y2,!y,C,xm,x,x,r"))]
+				"Cr ,m,C  ,!?ym,!?y,*Y2,!y,C,xm,x,x,r"))]
   "TARGET_64BIT && TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
@@ -124,9 +124,9 @@
 
 (define_insn "*movv2sf_internal_rex64"
   [(set (match_operand:V2SF 0 "nonimmediate_operand"
-				"=rm,r ,!?y,!?y ,m ,!y,Y2,x,x,x,m,r,x")
+				"=rm,r ,!?y,!?y ,m ,!y,*Y2,x,x,x,m,r,x")
         (match_operand:V2SF 1 "vector_move_operand"
-				"Cr ,m ,C  ,!?ym,!y,Y2,!y,C,x,m,x,x,r"))]
+				"Cr ,m ,C  ,!?ym,!y,*Y2,!y,C,x,m,x,x,r"))]
   "TARGET_64BIT && TARGET_MMX
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md	(revision 138553)
+++ config/i386/sse.md	(working copy)
@@ -4777,7 +4777,7 @@
   "")
 
 (define_insn "*sse2_storeq_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,r,r")
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,*r,r")
 	(vec_select:DI
 	  (match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o")
 	  (parallel [(const_int 0)])))]
@@ -4940,10 +4940,10 @@
    (set_attr "mode" "TI,V4SF,V2SF")])
 
 (define_insn "vec_concatv2di"
-  [(set (match_operand:V2DI 0 "register_operand"     "=Y2,?Y2,Y2,x,x,x")
+  [(set (match_operand:V2DI 0 "register_operand"     "=Y2 ,?Y2,Y2,x,x,x")
 	(vec_concat:V2DI
-	  (match_operand:DI 1 "nonimmediate_operand" "  m,*y ,0 ,0,0,m")
-	  (match_operand:DI 2 "vector_move_operand"  "  C,  C,Y2,x,m,0")))]
+	  (match_operand:DI 1 "nonimmediate_operand" " mY2,*y ,0 ,0,0,m")
+	  (match_operand:DI 2 "vector_move_operand"  " C  ,  C,Y2,x,m,0")))]
   "!TARGET_64BIT && TARGET_SSE"
   "@
    movq\t{%1, %0|%0, %1}
@@ -4956,10 +4956,10 @@
    (set_attr "mode" "TI,TI,TI,V4SF,V2SF,V2SF")])
 
 (define_insn "*vec_concatv2di_rex64_sse4_1"
-  [(set (match_operand:V2DI 0 "register_operand"     "=x,x,Yi,!x,x,x,x,x")
+  [(set (match_operand:V2DI 0 "register_operand"     "=x ,x ,Yi,!x,x,x,x,x")
 	(vec_concat:V2DI
-	  (match_operand:DI 1 "nonimmediate_operand" " 0,m,r ,*y,0,0,0,m")
-	  (match_operand:DI 2 "vector_move_operand"  "rm,C,C ,C ,x,x,m,0")))]
+	  (match_operand:DI 1 "nonimmediate_operand" " 0 ,mx,r ,*y,0,0,0,m")
+	  (match_operand:DI 2 "vector_move_operand"  " rm,C ,C ,C ,x,x,m,0")))]
   "TARGET_64BIT && TARGET_SSE4_1"
   "@
    pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
@@ -4975,10 +4975,10 @@
    (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF,V2SF")])
 
 (define_insn "*vec_concatv2di_rex64_sse"
-  [(set (match_operand:V2DI 0 "register_operand"     "=Y2,Yi,!Y2,Y2,x,x,x")
+  [(set (match_operand:V2DI 0 "register_operand"     "=Y2 ,Yi,!Y2,Y2,x,x,x")
 	(vec_concat:V2DI
-	  (match_operand:DI 1 "nonimmediate_operand" "  m,r ,*y ,0 ,0,0,m")
-	  (match_operand:DI 2 "vector_move_operand"  "  C,C ,C  ,Y2,x,m,0")))]
+	  (match_operand:DI 1 "nonimmediate_operand" " mY2,r ,*y ,0 ,0,0,m")
+	  (match_operand:DI 2 "vector_move_operand"  " C  ,C ,C  ,Y2,x,m,0")))]
   "TARGET_64BIT && TARGET_SSE"
   "@
    movq\t{%1, %0|%0, %1}
Index: testsuite/gcc.target/i386/pr36992-1.c
===================================================================
--- testsuite/gcc.target/i386/pr36992-1.c	(revision 0)
+++ testsuite/gcc.target/i386/pr36992-1.c	(revision 0)
@@ -0,0 +1,12 @@
+/* { dg-do compile }
+/* { dg-options "-O2 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (__m128i b)
+{
+  return _mm_move_epi64 (b);
+}
+
+/* { dg-final { scan-assembler-times "mov\[qd\]\[ \\t\]+.*%xmm" 1 } } */
Index: testsuite/gcc.target/i386/pr36992-2.c
===================================================================
--- testsuite/gcc.target/i386/pr36992-2.c	(revision 0)
+++ testsuite/gcc.target/i386/pr36992-2.c	(revision 0)
@@ -0,0 +1,12 @@
+/* { dg-do compile }
+/* { dg-options "-O0 -msse2" } */
+
+#include <emmintrin.h>
+
+__m128i
+test (__m128i b)
+{
+  return _mm_move_epi64 (b);
+}
+
+/* { dg-final { scan-assembler-not "%mm" } } */
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