Created attachment 29762 [details] testcase Attached sample worked fine on gcc 4.7 but gcc 4.8 ICE's on ARM -std=gnu99 -fgnu89-inline -c -march=armv5te -O2 is the compiler option set used /tmp/xx.i:3786:1: error: unrecognizable insn: } ^ (insn 516 515 12 16 (parallel [ (set (reg:SI 3 r3) (mem/c:SI (reg:SI 3 r3) [11 S4 A32])) (set (reg:SI 12 ip) (mem/c:SI (plus:SI (reg:SI 3 r3) (const_int 4 [0x4])) [11 S4 A32])) (set (reg/f:SI 13 sp) (mem/c:SI (plus:SI (reg:SI 3 r3) (const_int 8 [0x8])) [13 %sfp+-40 S4 A32])) ]) /tmp/xx.i:3735 -1 (expr_list:REG_ARGS_SIZE (const_int 0 [0]) (nil))) /tmp/xx.i:3786:1: internal compiler error: in extract_insn, at recog.c:2150 Please submit a full bug report, with preprocessed source if appropriate. See <http://gcc.gnu.org/bugs.html> for instructions.
Caused by r188738. http://gcc.gnu.org/ml/gcc-patches/2012-05/msg02073.html I'm looking into it.
The patch posted here http://patchwork.ozlabs.org/patch/237891/ Fixed the problem for my case of building elfutils
Author: gretay Date: Fri Apr 19 12:55:26 2013 New Revision: 198091 URL: http://gcc.gnu.org/viewcvs?rev=198091&root=gcc&view=rev Log: 2013-04-19 Greta Yorsh <Greta.Yorsh@arm.com> PR target/56797 * config/arm/arm.c (load_multiple_sequence): Require SP as base register for loads if SP is in the register list. Modified: trunk/gcc/ChangeLog trunk/gcc/config/arm/arm.c
Author: gretay Date: Wed Apr 24 10:43:41 2013 New Revision: 198220 URL: http://gcc.gnu.org/viewcvs?rev=198220&root=gcc&view=rev Log: 2013-04-24 Greta Yorsh <Greta.Yorsh@arm.com> Backported from mainline. PR target/56797 * config/arm/arm.c (load_multiple_sequence): Require SP as base register for loads if SP is in the register list. Modified: branches/gcc-4_8-branch/gcc/ChangeLog branches/gcc-4_8-branch/gcc/config/arm/arm.c
Fixed.