[hjl@gnu-6 gcc]$ cat z.c #define N 16 float b[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; float c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; float a[N]; void test (void) { int i; for (i = 0; i < N/2; i++) a[i] = b[2*i+1] * c[2*i+1]; } [hjl@gnu-6 gcc]$ ./xgcc -B./ -O2 -ftree-vectorize -mavx -S z.c [hjl@gnu-6 gcc]$ cat z.s .file "z.c" .text .p2align 4,,15 .globl test .type test, @function test: .LFB0: .cfi_startproc vxorps %xmm0, %xmm0, %xmm0 pushq %rbp .cfi_def_cfa_offset 16 movq %rsp, %rbp .cfi_offset 6, -16 .cfi_def_cfa_register 6 vmovaps %ymm0, a(%rip) leave .cfi_def_cfa 7, 8 ret .cfi_endproc The probem is "vec_extract_evenv8sf" and "vec_extract_oddv8sf" call expand_vec_perm_even_odd_1 which calls expand_vselect and expand_vec_perm_vpermil without checking return values. For V4SF, those functions return false.
Subject: Bug 44180 Author: hjl Date: Mon May 17 23:47:44 2010 New Revision: 159519 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=159519 Log: Properly implement extract even/odd elements for V8SF. gcc/ 2010-05-18 H.J. Lu <hongjiu.lu@intel.com> PR target/44180 * config/i386/i386.c (expand_vec_perm_even_odd_1): Rewritten for V8SFmode. gcc/testsuite/ 2010-05-18 H.J. Lu <hongjiu.lu@intel.com> PR target/44180 * gcc.target/i386/pr44180.c: New. Added: branches/vect256/gcc/testsuite/gcc.target/i386/pr44180.c Modified: branches/vect256/gcc/ChangeLog.vect256 branches/vect256/gcc/config/i386/i386.c branches/vect256/gcc/testsuite/ChangeLog.vect256
Author: hjl Date: Wed Oct 13 21:20:07 2010 New Revision: 165436 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=165436 Log: Addd 256bit AVX vectorizer patterns. 2010-10-13 H.J. Lu <hongjiu.lu@intel.com> * config/i386/i386.c (ix86_build_const_vector): Check vector mode instead of scalar mode. (ix86_build_signbit_mask): Likewise. (ix86_expand_fp_absneg_operator): Updated. (ix86_expand_copysign): Likewise. (ix86_expand_int_vcond): Likewise. (ix86_emit_swdivsf): Likewise. (ix86_sse_copysign_to_positive): Likewise. (ix86_expand_sse_fabs): Likewise. * config/i386/i386.md (fixuns_trunc<mode>si2): Likewise. * config/i386/sse.md (copysign<mode>3): Likewise. (sse2_cvtudq2ps): Likewise. (vec_unpacku_float_hi_v4si): Likewise. (vec_unpacku_float_lo_v4si): Likewise. * config/i386/i386.c (ix86_builtins): Add IX86_BUILTIN_CPYSGNPS256 and IX86_BUILTIN_CPYSGNPD256. (bdesc_args): Likewise. (ix86_builtin_vectorized_function): Support IX86_BUILTIN_CPYSGNPS256, IX86_BUILTIN_CPYSGNPD256, IX86_BUILTIN_SQRTPD256, IX86_BUILTIN_SQRTPS_NR256, and IX86_BUILTIN_CVTPS2DQ256. (ix86_builtin_reciprocal): Support IX86_BUILTIN_SQRTPS_NR256. * config/i386/sse.md (STORENT_MODE): New. (VEC_FLOAT_MODE): Likewise. (VEC_EXTRACT_MODE): Likewise. (*avx_cvtdq2pd256_2): Likewise. (vec_pack_trunc_v4df): Likewise. (vec_interleave_highv8sf): Likewise. (vec_interleave_lowv8sf): Likewise. (storent<mode>): Macroized. (<code><mode>2: absneg): Likewise. (copysign<mode>3): Likewise. (vec_extract<mode>): Likewise. PR target/44180 * config/i386/i386.c (expand_vec_perm_even_odd_1): Rewritten for V8SFmode. 2010-10-13 Richard Guenther <rguenther@suse.de> H.J. Lu <hongjiu.lu@intel.com> * config/i386/sse.md (reduc_splus_v8sf): Add. (reduc_splus_v4df): Likewise. (vec_unpacks_hi_v8sf): Likewise. (vec_unpacks_lo_v8sf): Likewise. (*avx_cvtps2pd256_2): Likewise. (vec_unpacks_float_hi_v8si): Likewise. (vec_unpacks_float_lo_v8si): Likewise. (vec_interleave_highv4df): Likewise. (vec_interleave_lowv4df): Likewise. Modified: trunk/gcc/ChangeLog trunk/gcc/config/i386/i386.c trunk/gcc/config/i386/i386.md trunk/gcc/config/i386/sse.md
Author: hjl Date: Thu Oct 14 02:11:59 2010 New Revision: 165445 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=165445 Log: Add a testcase for PR target/44180. 2010-10-13 H.J. Lu <hongjiu.lu@intel.com> PR target/44180 * gcc.target/i386/pr44180.c: New. Added: trunk/gcc/testsuite/gcc.target/i386/pr44180.c Modified: trunk/gcc/testsuite/ChangeLog
Fixed.