There is no mode class to describe a SIMD condition code register.
Is there a reason behind why you want this? SIMD CC modes seems a bit weird .
(In reply to comment #1) > Is there a reason behind why you want this? SIMD CC modes seems a bit weird The MXP architecture has a SIMD CC register that is pretty close to CC0. I.e. some moves and adds can be done witout affecting this register, but some simply can't.
I still don't understand what you mean by that. Do you mean the registers are vector based and the instructions effect the conditional register and that conditional register has slots (elements) that correspond to the vector slots (elements)? Still having a vector mode of CCmode seems weird.
(In reply to comment #3) > I still don't understand what you mean by that. Do you mean the registers are > vector based and the instructions effect the conditional register and that > conditional register has slots (elements) that correspond to the vector slots > (elements)? Exactly. The conditiona register is known as V8CCImode for ordinary integer instructions, V8CCZNmode if only N/Z flags matter, and V8CCZmode when only the Z falg is relevant. You can copy it from/to a general purpose vector register, in which case it looks like a V8PHImode register with 6 valid bits per element. There are also use cases where it acts as having 32 bit partial elements. > Still having a vector mode of CCmode seems weird. Actually, it makes more sense than a scalar CCmode register. The limited clock frequency is compensated for by higher throughput per cycle. Van Neumann would have said that having a processor with 4 or 5 different types of physical memory (L1 Dcache, L1 Icache, L2 cache, maybe L3 cache, main memory) seems weird.
patch is here: http://gcc.gnu.org/ml/gcc-patches/2009-03/msg00259.html