We expand __builtin___clear_cache() to a 'synci' instruction on ISA_HAS_SYNCI systems, which invalidates the icache only on the local CPU. On an SMP system, the caches on all CPUs should be invalidated. To achieve this we need to drop back to the old way of doing things by using the cache flush system call.
I am working on a patch.
Subject: Bug 39079 Author: daney Date: Fri Jul 10 22:49:52 2009 New Revision: 149500 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=149500 Log: 2009-07-10 David Daney <ddaney@caviumnetworks.com> PR target/39079 * testsuite/gcc.target/mips/mips.exp: Make -msynci a known option. * gcc.target/mips/clear-cache-1.c (dg-options): Add -msynci. 2009-07-10 David Daney <ddaney@caviumnetworks.com> PR target/39079 * config.gcc (supported_defaults): Add synci. (with_synci): Add validation. (all_defaults): Add synci. * config/mips/mips.md (clear_cache): Use TARGET_SYNCI instead of ISA_HAS_SYNCI. (synci): Same. * config/mips/mips.opt (msynci): New option. * config/mips/mips.c (mips_override_options): Warn on use of -msynci for targets that do now support it. * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for msynci. * gcc/doc/invoke.texi (-msynci): Document the new option. * doc/install.texi (--with-synci): Document the new option. Modified: trunk/gcc/ChangeLog trunk/gcc/config.gcc trunk/gcc/config/mips/mips.c trunk/gcc/config/mips/mips.h trunk/gcc/config/mips/mips.md trunk/gcc/config/mips/mips.opt trunk/gcc/doc/install.texi trunk/gcc/doc/invoke.texi trunk/gcc/testsuite/ChangeLog trunk/gcc/testsuite/gcc.target/mips/clear-cache-1.c trunk/gcc/testsuite/gcc.target/mips/mips.exp
Fixed by the patch.