This test case causes two different internal compiler errors in GCC when compiled with "-m32 -maltivec", with VECSIZE either 2 or 8: __attribute__ ((vector_size (VECSIZE))) unsigned char v1, v2, v3; void vxor (void) { v1 = v2 ^ v3; } Using a cross compiler on i686-linux with today's mainline: laptop% $XGCC -m32 -maltivec -DVECSIZE=2 -c bug2.c bug2.c: In function 'vxor': bug2.c:9: internal compiler error: in operand_subword_force, at /emit-rtl.c:1384Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://gcc.gnu.org/bugs.html> for instructions. laptop% $XGCC -m32 -maltivec -DVECSIZE=8 -c bug2.c bug2.c: In function 'vxor': bug2.c:10: internal compiler error: in simplify_subreg, at /simplify-rtx.c:3572 Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://gcc.gnu.org/bugs.html> for instructions. There is no ICE when VECSIZE is 4. Hardware-supported AltiVec vectors are 16 bytes, so all of these are smaller than hardware-supported vectors. The larger testcase compiles and runs as expected when hardware vector support is not enabled.
Hmm this works on ppc-darwin.
Confirmed with -DVECSIZE=2, here the backtrace: ---------------------------------------------------------------------------------------- Program received signal SIGSEGV, Segmentation fault. 0x08164577 in extract_fixed_bit_field (tmode=SImode, op0=0x0, offset=0, bitsize=16, bitpos=16, target=0x0, unsignedp=1) at ../../gcc/gcc/expmed.c:1674 1674 if (GET_CODE (op0) == SUBREG || REG_P (op0)) #0 0x08164577 in extract_fixed_bit_field (tmode=SImode, op0=0x0, offset=0, bitsize=16, bitpos=16, target=0x0, unsignedp=1) at ../../gcc/gcc/expmed.c:1674 #1 0x08165021 in extract_split_bit_field (op0=0xb7b3c360, bitsize=32, bitpos=16, unsignedp=0) at ../../gcc/gcc/expmed.c:1920 #2 0x081645f4 in extract_fixed_bit_field (tmode=SImode, op0=0xb7b3c360, offset=0, bitsize=32, bitpos=16, target=0xb7b3c330, unsignedp=0) at ../../gcc/gcc/expmed.c:1678 #3 0x0816449d in extract_bit_field (str_rtx=0x9, bitsize=32, bitnum=0, unsignedp=0, target=0xb7b3c330, mode=SImode, tmode=SImode) at ../../gcc/gcc/expmed.c:1622 #4 0x081795ba in expand_expr_real_1 (exp=0xb7b3b050, target=0xb7b3c330, tmode=SImode, modifier=EXPAND_NORMAL, alt_rtl=0xbfffe808) at ../../gcc/gcc/expr.c:7038 #5 0x08177a24 in expand_expr_real (exp=0xb7b3b050, target=0xb7b3c330, tmode=SImode, modifier=EXPAND_NORMAL, alt_rtl=0xbfffe808) at ../../gcc/gcc/expr.c:6205 #6 0x08173269 in store_expr (exp=0xb7b3b050, target=0xb7b3c330, call_param_p=0) at ../../gcc/gcc/expr.c:3887 #7 0x08172ed3 in expand_assignment (to=0xb7b42f80, from=0xb7b3b050) at ../../gcc/gcc/expr.c:3766 #8 0x0817bbed in expand_expr_real_1 (exp=0xb7abd4ec, target=0x0, tmode=VOIDmode, modifier=EXPAND_NORMAL, alt_rtl=0x0) at ../../gcc/gcc/expr.c:7987 #9 0x081779ee in expand_expr_real (exp=0xb7abd4ec, target=0xb7abc300, tmode=VOIDmode, modifier=EXPAND_NORMAL, alt_rtl=0x0) at ../../gcc/gcc/expr.c:6199 #10 0x08298263 in expand_expr_stmt (exp=0xb7abd4ec) at expr.h:493 #11 0x082bda71 in expand_gimple_basic_block (bb=0xb7b42c98, dump_file=0xb7b3b208) at ../../gcc/gcc/cfgexpand.c:1133 #12 0x082bdebb in tree_expand_cfg () at ../../gcc/gcc/cfgexpand.c:1306 #13 0x0809d4f4 in execute_one_pass (pass=0x84d4de0) at ../../gcc/gcc/tree-optimize.c:508 #14 0x0809d5bb in execute_pass_list (pass=0x84d4de0) at ../../gcc/gcc/tree-optimize.c:545 #15 0x0809d797 in tree_rest_of_compilation (fndecl=0xb7b425d0) at ../../gcc/gcc/tree-optimize.c:640 #16 0x08059682 in c_expand_body (fndecl=0xb7b425d0) at ../../gcc/gcc/c-decl.c:6363 #17 0x082e004c in cgraph_expand_function (node=0xb7b42744) at ../../gcc/gcc/cgraphunit.c:822 #18 0x082df625 in cgraph_assemble_pending_functions () at ../../gcc/gcc/cgraphunit.c:305 #19 0x082df727 in cgraph_finalize_function (decl=0xb7b425d0, nested=0 '\0') at ../../gcc/gcc/cgraphunit.c:388 #20 0x0805963a in finish_function () at ../../gcc/gcc/c-decl.c:6335 #21 0x0804a412 in yyparse () at c-parse.y:401 #22 0x0804f80e in c_parse_file () at c-parse.y:2908 #23 0x0807eebe in c_common_parse_file (set_yydebug=32) at ../../gcc/gcc/c-opts.c:1095 #24 0x082a0485 in compile_file () at ../../gcc/gcc/toplev.c:986 #25 0x082a1cde in do_compile () at ../../gcc/gcc/toplev.c:2074 #26 0x082a1d3c in toplev_main (argc=32, argv=0xbffff564) at ../../gcc/gcc/toplev.c:2106 #27 0x0808c1f8 in main (argc=32, argv=0x20) at ../../gcc/gcc/main.c:35 ----------------------------------------------------------------------------------------
3.4.3 rejects -DVECSIZE=2 code with "error: no vector mode with the size and type specified could be found"
I think this has been fixed on the mainline but I don't know for sure.
I just tried with today's mainline for powerpc64-unknown-linux-gnu and get the same two ICEs as were reported originally. The 3.4 branch gives the error that Serge noted for -DVECSIZE=2 and accepts -DVECSIZE=8. This is a regression, but no one seems to expect generic vectors to actually work.
This is weird in that it works on ppc-darwin, maybe the altivec ABI is changing something or the just the ABI difference.
Subject: Bug 17961 CVSROOT: /cvs/gcc Module name: gcc Changes by: aldyh@gcc.gnu.org 2005-06-10 17:04:09 Modified files: gcc/config/rs6000: sysv4.h linux64.h Added files: gcc/testsuite/gcc.dg: simd-3.c Log message: PR 17961 * config/rs6000/sysv4.h (ROUND_TYPE_ALIGN): Remove. * config/rs6000/linux64.h (ROUND_TYPE_ALIGN): Remove vector check. * testsuite/gcc.dg/simd-3.c: New. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/sysv4.h.diff?cvsroot=gcc&r1=1.163&r2=1.164 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/linux64.h.diff?cvsroot=gcc&r1=1.78&r2=1.79 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/testsuite/gcc.dg/simd-3.c.diff?cvsroot=gcc&r1=NONE&r2=1.1
Fixed in mainline. Waiting for 4.0 freeze to be lifted to commit there. http://gcc.gnu.org/ml/gcc-patches/2005-06/msg00959.html
Subject: Bug 17961 CVSROOT: /cvs/gcc Module name: gcc Branch: gcc-4_0-branch Changes by: aldyh@gcc.gnu.org 2005-07-08 19:34:41 Modified files: gcc : ChangeLog gcc/config/rs6000: sysv4.h linux64.h Added files: gcc/testsuite/gcc.dg: simd-3.c Log message: PR 17961 * config/rs6000/sysv4.h (ROUND_TYPE_ALIGN): Remove. * config/rs6000/linux64.h (ROUND_TYPE_ALIGN): Remove vector check. * testsuite/gcc.dg/simd-3.c: New. Patches: http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&only_with_tag=gcc-4_0-branch&r1=2.7592.2.302&r2=2.7592.2.303 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/sysv4.h.diff?cvsroot=gcc&only_with_tag=gcc-4_0-branch&r1=1.158&r2=1.158.4.1 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/rs6000/linux64.h.diff?cvsroot=gcc&only_with_tag=gcc-4_0-branch&r1=1.74.10.1&r2=1.74.10.2 http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/testsuite/gcc.dg/simd-3.c.diff?cvsroot=gcc&only_with_tag=gcc-4_0-branch&r1=NONE&r2=1.1.8.1