Looking for status of SIMD implementation

[Matthias Kretz]

Well great, now I accidentally sent the mail without context... so here's what 
I answered :)

On Donnerstag, 24. Juni 2021 07:17:46 CEST you wrote:
> Hi Matthias,
> Sorry for the late reply.
> 
> We are investigating the support of SVE in SIMD (and RISC-V V
> extension in the future), as you may know, it's a difficult task
> because of the VLA programming model.  One decision needs to be made
> is whether/how we implement SVE support in the VLA way, or fixed
> vector size way.
> 
> ARM(Richard Sandiford) proposed sizeless type extension
> [http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2018/p1101r0.html],
> but seems it won't be incorporated in near future.  Without this
> extension, I don't see any practical way to support SVE/VLA in SIMD,
> so we are left with the fixed vector size way.  Even with fixed vector
> size, there are quite a lot of difficulties that need to be resolved,
> for example, SVE has very limited capacity manipulating predicate
> registers while std::bitset and SIMD::_BitMask are implemented as
> packed bits.
> 
> I am still working on the prototype supporting SVE using the fixed
> vector size method.  I am wondering if you have any plans for SVE/RVV?
>  Or any comments about the idea.
> 
> Thanks,
> bin

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 Dr. Matthias Kretz                           https://mattkretz.github.io
 GSI Helmholtz Centre for Heavy Ion Research               https://gsi.de
 std::experimental::simd              https://github.com/VcDevel/std-simd
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