Fw: [patch] Make std::tr1::shared_ptr thread-safe.

[Peter Dimov]

Alexander Terekhov wrote:
> On Apr 1, 2005 7:10 PM, Peter Dimov <pdimov@mmltd.net> wrote:
>> Alexander Terekhov wrote:
>>>> or powerpc:
>>>
>>> Well, see
>>>
>>> http://sourceware.org/cgi-bin/cvsweb.cgi/libc/sysdeps/powerpc/bits/atomic.h?cvsroot=glibc
>>
>> I see no "release" barriers in exchange_and_add or the decrements,
>> only an "acquire if zero" in decrement_if_positive.
>
> I meant __arch_compare_and_exchange_val_32_acq() and
> __arch_compare_and_exchange_val_32_rel() which illustrates placement
> and barrier instruction for acquire and release respectively. Fully-fenced
> stuff needs both.

Yes, thanks, leading sync and trailing isync. I actually knew what you 
meant. This was more a response to:

Paolo Carlini wrote:

> Ok, noted. Can I generalize that in glibc we can find the fully-fenced
> implementations of exchange_and_add that we are looking for?

Almost. ;-) The pieces of the puzzle are there, we just need to put them 
together.