locking problem with mips atomicity
Michael Eager
eager@mvista.com
Thu Mar 18 11:03:00 GMT 2004
Richard Henderson wrote:
>
> On Wed, Mar 17, 2004 at 02:45:08PM -0800, Michael Eager wrote:
> > + "ll %0,0(%2)\n\t"
> > + "addu %1,%3,%0\n\t"
> > + "sc %1,0(%2)\n\t"
> > ".set pop\n\t"
> > "beqz %1,1b\n\t"
> > "/* End exchange & add */"
> > + : "=&r"(__result), "=&r"(__tmp), "+r"(__mem)
>
> Why the in-out constraint on __mem? You don't modify %2.
OK, changed it to only input.
--
Michael Eager eager@mvista.com 408-328-8426
MontaVista Software, Inc. 1237 E. Arques Ave., Sunnyvale, CA 94085
-------------- next part --------------
2004-03-16 Michael Eager <eager@mvista.com>
* config/cpu/mips/atomicity.h: Prevent reg loads
between LL and SC instructions.
Index: ./libstdc++-v3/config/cpu/mips/atomicity.h
===================================================================
RCS file: /cvs/gcc/gcc/libstdc++-v3/config/cpu/mips/atomicity.h,v
retrieving revision 1.9
diff -u -r1.9 atomicity.h
--- ./libstdc++-v3/config/cpu/mips/atomicity.h 27 Feb 2004 00:49:48 -0000 1.9
+++ ./libstdc++-v3/config/cpu/mips/atomicity.h 18 Mar 2004 01:01:26 -0000
@@ -44,14 +44,15 @@
#if _MIPS_SIM == _ABIO32
".set mips2\n\t"
#endif
- "ll %0,%3\n\t"
- "addu %1,%4,%0\n\t"
- "sc %1,%2\n\t"
+ "ll %0,0(%2)\n\t"
+ "addu %1,%3,%0\n\t"
+ "sc %1,0(%2)\n\t"
".set pop\n\t"
"beqz %1,1b\n\t"
"/* End exchange & add */"
- : "=&r"(__result), "=&r"(__tmp), "=m"(*__mem)
- : "m" (*__mem), "r"(__val));
+ : "=&r"(__result), "=&r"(__tmp)
+ : "r"(__mem), "r"(__val)
+ : "memory" );
return __result;
}
@@ -69,13 +70,14 @@
#if _MIPS_SIM == _ABIO32
".set mips2\n\t"
#endif
- "ll %0,%2\n\t"
- "addu %0,%3,%0\n\t"
- "sc %0,%1\n\t"
+ "ll %0,0(%1)\n\t"
+ "addu %0,%2,%0\n\t"
+ "sc %0,0(%1)\n\t"
".set pop\n\t"
"beqz %0,1b\n\t"
"/* End atomic add */"
- : "=&r"(__result), "=m"(*__mem)
- : "m" (*__mem), "r"(__val));
+ : "=&r"(__result)
+ : "r"(__mem), "r"(__val)
+ : "memory" );
}
} // namespace __gnu_cxx
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