[gcc r16-4453] Daily bump.
GCC Administrator
gccadmin@gcc.gnu.org
Thu Oct 16 00:22:30 GMT 2025
https://gcc.gnu.org/g:b9c253795e86ac507bd1a607c39a180c41b8051e
commit r16-4453-gb9c253795e86ac507bd1a607c39a180c41b8051e
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Thu Oct 16 00:21:56 2025 +0000
Daily bump.
Diff:
---
ChangeLog | 5 ++
gcc/ChangeLog | 136 ++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/testsuite/ChangeLog | 42 +++++++++++++++
libgomp/ChangeLog | 12 +++++
libstdc++-v3/ChangeLog | 30 +++++++++++
6 files changed, 226 insertions(+), 1 deletion(-)
diff --git a/ChangeLog b/ChangeLog
index 687470279323..241d28e6fd96 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,8 @@
+2025-10-15 Basil Milanich <bmilanich@gmail.com>
+
+ * Makefile.tpl (distclean): Remove extraenous semicolon.
+ * Makefile.in: Rebuilt.
+
2025-10-11 Ben Boeckel <ben.boeckel@kitware.com>
* config-ml.in: Update patch email address.
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8a7cb97ad3e9..3df799b73e2c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,139 @@
+2025-10-15 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/121468
+ PR tree-optimization/121206
+ PR tree-optimization/122200
+ * value-range.cc (irange_bitmask::range_from_mask): New.
+ (irange::snap): Add explicit overflow flag.
+ (irange::snap_subranges): Use overflow flag.
+ (irange::set_range_from_bitmask): Use range_from_mask.
+ (test_irange_snap_bounds): Adjust for improved ranges.
+ * value-range.h (irange::range_from_mask): Add prototype.
+ (irange::snap): Adjust prototype.
+
+2025-10-15 Tobias Burnus <tburnus@baylibre.com>
+
+ * config/gcn/gcn-devices.def (gfx942, gfx950): Set generic name
+ to GFX9_4_GENERIC.
+ * config/gcn/t-omp-device: Include generic names for OpenMP's
+ ISA trait.
+
+2025-10-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
+
+ * print-tree.cc (print_node): Print out clique/base
+ for MEM_REF and TARGET_MEM_REF.
+
+2025-10-15 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/118460
+ * config/arm/arm.cc (arm_canonicalize_comparison): For floating-
+ point comparisons, swap the operand order if that will be more
+ likely to produce a comparison that can be used with VSEL.
+ (arm_validize_comparison): Make sure that HFmode comparisons
+ are compatible with VSEL.
+
+2025-10-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
+
+ PR tree-optimization/122037
+ * tree-ssa-dce.cc (eliminate_unnecessary_stmts): Remove
+ __builtin_stack_save when the lhs is unused.
+
+2025-10-15 Alice Carlotti <alice.carlotti@arm.com>
+
+ * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
+ * config/aarch64/aarch64.cc (F_ARCHEXT): Delete flag.
+ * config/aarch64/aarch64.h
+ (AARCH64_FL_AMU): Delete unused macro.
+ (AARCH64_FL_SCXTNUM): Ditto.
+ (AARCH64_FL_ID_PFR2): Ditto.
+ (AARCH64_FL_AIE): Ditto.
+ (AARCH64_FL_DEBUGv8p9): Ditto.
+ (AARCH64_FL_FGT2): Ditto.
+ (AARCH64_FL_PFAR): Ditto.
+ (AARCH64_FL_PMUv3_ICNTR): Ditto.
+ (AARCH64_FL_PMUv3_SS): Ditto.
+ (AARCH64_FL_PMUv3p9): Ditto.
+ (AARCH64_FL_S1PIE): Ditto.
+ (AARCH64_FL_S1POE): Ditto.
+ (AARCH64_FL_S2PIE): Ditto.
+ (AARCH64_FL_S2POE): Ditto.
+ (AARCH64_FL_SCTLR2): Ditto.
+ (AARCH64_FL_SEBEP): Ditto.
+ (AARCH64_FL_SPE_FDS): Ditto.
+ (AARCH64_FL_TCR2): Ditto.
+
+2025-10-15 Sebastian Pop <spop@nvidia.com>
+
+ * doc/invoke.texi (ftree-parallelize-loops): Update.
+ * common.opt (ftree-parallelize-loops): Add alias that maps to
+ special value INT_MAX for runtime thread detection.
+ * tree-parloops.cc (create_parallel_loop): Use INT_MAX for runtime
+ detection. Call gimple_build_omp_parallel without building a
+ OMP_CLAUSE_NUM_THREADS clause.
+ (gen_parallel_loop): For auto-detection, use a conservative
+ estimate of 2 threads.
+ (parallelize_loops): Same.
+
+2025-10-15 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR target/122189
+ * config/arm/iterators.md (VxCIQ_carry, VxCIQ_M_carry, VxCQ_carry)
+ (VxCQ_M_carry): New iterators.
+ * config/arm/mve.md (get_fpscr_nzcvqc, set_fpscr_nzcvqc): Use
+ unspec instead of unspec_volatile.
+ (vadciq, vadciq_m, vadcq, vadcq_m): Use vfpcc in operation. Use a
+ different unspec code for carry calcultation.
+ * config/arm/unspecs.md (VADCQ_U_carry, VADCQ_M_U_carry)
+ (VADCQ_S_carry, VADCQ_M_S_carry, VSBCIQ_U_carry ,VSBCIQ_S_carry
+ ,VSBCIQ_M_U_carry ,VSBCIQ_M_S_carry ,VSBCQ_U_carry ,VSBCQ_S_carry
+ ,VSBCQ_M_U_carry ,VSBCQ_M_S_carry ,VADCIQ_U_carry
+ ,VADCIQ_M_U_carry ,VADCIQ_S_carry ,VADCIQ_M_S_carry): New unspec
+ codes.
+
+2025-10-15 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR rtl-optimization/122266
+ * combine.cc (struct reg_stat_type): Change types of sign_bit_copies
+ and last_set_sign_bit_copies to unsigned short, to avoid overflows
+ on TImode (and wider) values.
+
+2025-10-15 Jan Hubicka <hubicka@ucw.cz>
+
+ * auto-profile.cc (scale_bb_profile): Use
+ profile_count::max_prefer_initialized.
+ (afdo_adjust_guessed_profile): Likewise.
+ * bb-reorder.cc (edge_order): Do not use max.
+ * cfghooks.cc (merge_blocks): Likewise.
+ * ipa-fnsummary.cc (param_change_prob): Likewise.
+ * ipa-inline-transform.cc (inline_transform): Likewise.
+ * predict.cc (update_max_bb_count): Likewise.
+ (estimate_bb_frequencies): Likewise.
+ (rebuild_frequencies): Likewise.
+ * tree-ssa-loop-unswitch.cc (struct unswitch_predicate): Likewise.
+ * profile-count.h (profile_count::max): Rename to
+ (profile_count::max_prefer_initialized): this; update handling
+ of qualities.
+
+2025-10-15 Haochen Jiang <haochen.jiang@intel.com>
+
+ * common/config/i386/cpuinfo.h
+ (get_intel_cpu): Handle Wildcat Lake.
+ * common/config/i386/i386-common.cc (processor_name):
+ Add Wildcat Lake.
+ * doc/invoke.texi: Ditto.
+
+2025-10-15 Haochen Jiang <haochen.jiang@intel.com>
+
+ * config/i386/i386.h
+ (PTA_PANTHERLAKE): Remove PREFETCHI.
+ (PTA_DIAMONDRAPIDS): Remove USER_MSR.
+ * doc/invoke.texi: Correct documentation.
+
+2025-10-15 Pan Li <pan2.li@intel.com>
+
+ * config/riscv/autovec-opt.md: Take concrete op instead
+ of any_widen_binop for vwaddu/vwsubu wx combine.
+
2025-10-14 Richard Biener <rguenther@suse.de>
* tree-vectorizer.h (REDUC_GROUP_FIRST_ELEMENT,
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 0535efab6596..8ca925d3df4e 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20251015
+20251016
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ca170a1518ce..d910bc0f188c 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,45 @@
+2025-10-15 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/121468
+ PR tree-optimization/121206
+ PR tree-optimization/122200
+ * gcc.dg/pr121468.c: New.
+ * gcc.dg/pr122200.c: New.
+
+2025-10-15 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/118460
+ * gcc.target/arm/armv8_2-fp16-move-1.c: Adjust expected output.
+ * gcc.target/arm/armv8_2-fp16-move-2.c: Likewise.
+
+2025-10-15 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
+
+ PR tree-optimization/122037
+ * gcc.dg/tree-ssa/vla-1.c: New test.
+
+2025-10-15 Alice Carlotti <alice.carlotti@arm.com>
+
+ * gcc.target/aarch64/acle/rwsr-armv8p9.c: Fix incorrect encoding.
+
+2025-10-15 Sebastian Pop <spop@nvidia.com>
+
+ * gcc.dg/autopar/runtime-auto.c: New test.
+
+2025-10-15 Christophe Lyon <christophe.lyon@linaro.org>
+
+ PR target/122189
+ * gcc.target/arm/mve/intrinsics/vadcq-check-carry.c: New test.
+ * gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Adjust instructions
+ order.
+ * gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Likewise.
+ * gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Likewise.
+
+2025-10-15 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR rtl-optimization/122266
+ * gcc.target/i386/pr122266.c: New test case.
+
2025-10-14 Patrick Palka <ppalka@redhat.com>
PR c++/122192
diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 8b9f0ff9c724..fae7455f3e50 100644
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,15 @@
+2025-10-15 Tobias Burnus <tburnus@baylibre.com>
+
+ * libgomp.texi (OpenMP Context Selectors): Add note that there is
+ currently an exact match between ISA and compilation, ignoring
+ compatibilities in both ways.
+ * testsuite/libgomp.c/declare-variant-4.h: Add missing variant
+ functions for specific and generic AMD GPUs.
+ * testsuite/libgomp.c/declare-variant-4-gfx10-3-generic.c: New test.
+ * testsuite/libgomp.c/declare-variant-4-gfx11-generic.c: New test.
+ * testsuite/libgomp.c/declare-variant-4-gfx9-4-generic.c: New test.
+ * testsuite/libgomp.c/declare-variant-4-gfx9-generic.c: New test.
+
2025-10-10 Tobias Burnus <tburnus@baylibre.com>
* plugin/plugin-gcn.c (is_integrated_apu): New; currently '#if 0'.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index c21614723354..044919832828 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,33 @@
+2025-10-15 Jonathan Wakely <jwakely@redhat.com>
+
+ * python/libstdcxx/v6/printers.py (StdStacktraceEntryPrinter):
+ New printer for std::stacktrace_entry.
+ (StdStacktracePrinter): New printer for std::basic_stacktrace.
+
+2025-10-15 Jonathan Wakely <jwakely@redhat.com>
+
+ * include/std/stacktrace (basic_stacktrace::current): Call
+ _M_trim before returning.
+ (basic_stacktrace::_M_trim): New member function.
+
+2025-10-15 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/122293
+ * include/bits/chrono.h (__to_timeout_timespec): Fix
+ preprocessor condition to match the conditions under which
+ callers of this function are defined.
+ * include/bits/this_thread_sleep.h: Remove unused include.
+
+2025-10-15 Chris Johns <chrisj@rtems.org>
+
+ * configure: Regenerate.
+ * configure.ac (newlib, *-rtems*): Add HAVE_SYS_IOCTL_H,
+ HAVE_SYS_STAT_H, HAVE_SYS_TYPES_H, HAVE_S_ISREG, HAVE_UNISTD_H,
+ HAVE_UNLINKAT, _GLIBCXX_USE_CHMOD, _GLIBCXX_USE_MKDIR,
+ _GLIBCXX_USE_CHDIR, _GLIBCXX_USE_GETCWD, _GLIBCXX_USE_UTIME,
+ _GLIBCXX_USE_LINK, _GLIBCXX_USE_READLINK, _GLIBCXX_USE_SYMLINK,
+ _GLIBCXX_USE_TRUNCATE and _GLIBCXX_USE_FDOPENDIR.
+
2025-10-14 Mike Crowe <mac@mcrowe.com>
PR libstdc++/116586
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