[gcc r16-3556] Daily bump.
GCC Administrator
gccadmin@gcc.gnu.org
Thu Sep 4 00:21:19 GMT 2025
https://gcc.gnu.org/g:a803d5b9cd37bb5440e96ee61c2db7d5b990ed53
commit r16-3556-ga803d5b9cd37bb5440e96ee61c2db7d5b990ed53
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Thu Sep 4 00:20:48 2025 +0000
Daily bump.
Diff:
---
ChangeLog | 4 ++
gcc/ChangeLog | 129 ++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cp/ChangeLog | 6 +++
gcc/fortran/ChangeLog | 7 +++
gcc/testsuite/ChangeLog | 102 ++++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 30 +++++++++++
7 files changed, 279 insertions(+), 1 deletion(-)
diff --git a/ChangeLog b/ChangeLog
index 75f768f7b902..a0a96bcc9e9b 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2025-09-03 Alice Carlotti <alice.carlotti@arm.com>
+
+ * MAINTAINERS: Add myself as an aarch64 port reviewer.
+
2025-08-28 Yuao Ma <c8ef@outlook.com>
* MAINTAINERS: add myself to write after approval
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 19da37a3838f..4d8aa47bed81 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,132 @@
+2025-09-03 Kuan-Lin Chen <rufus@andestech.com>
+
+ * config/riscv/andes.def: Add nds_fcvt_s_bf16 and nds_fcvt_bf16_s.
+ * config/riscv/riscv.md (truncsfbf2): Add TARGET_XANDESBFHCVT support.
+ (extendbfsf2): Ditto.
+ * config/riscv/riscv-builtins.cc: New AVAIL andesbfhcvt.
+ Add new define RISCV_ATYPE_BF and RISCV_ATYPE_SF.
+ * config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
+
+2025-09-03 Kuan-Lin Chen <rufus@andestech.com>
+
+ * config/riscv/constraints.md (Ou07): New constraint.
+ (ads_Bext): New constraint.
+ * config/riscv/iterators.md (ANYLE32): New iterator.
+ (sizen): New iterator.
+ (sh_limit): New iterator.
+ (sh_bit): New iterator.
+ (cs): New iterator.
+ * config/riscv/predicates.md (ads_branch_bbcs_operand): New predicate.
+ (ads_branch_bimm_operand): New predicate.
+ (ads_imm_extract_operand): New predicate.
+ (ads_extract_size_imm_si): New predicate.
+ (ads_extract_size_imm_di): New predicate.
+ (const_int5_operand): New predicate.
+ * config/riscv/riscv-builtins.cc:
+ Add new AVAIL andesperf32 and andesperf64.
+ Add new define RISCV_ATYPE_DI.
+ * config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
+ * config/riscv/riscv.cc
+ (riscv_extend_cost): Cost for pattern 'bfo'.
+ (riscv_rtx_costs): Cost for XAndesperf extension.
+ * config/riscv/riscv.md: Add support for XAndesperf to patterns
+ zero_extendsidi2_internal, zero_extendhi2, extendsidi2_internal,
+ extend<SHORT:mode><SUPERQI:mode>2, <any_extract:optab><GPR:mode>3
+ and branch_on_bit.
+ * config/riscv/vector-iterators.md
+ (sz): Add sign_extract and zero_extract.
+ * config/riscv/andes.def: New file for vender Andes.
+ * config/riscv/andes.md: New file for vender Andes.
+
+2025-09-03 Kuan-Lin Chen <rufus@andestech.com>
+
+ * config/riscv/riscv-ext.def: Include riscv-ext-andes.def.
+ * config/riscv/riscv-ext.opt (riscv_xandes_subext): New variable.
+ (XANDESPERF) : New mask.
+ (XANDESBFHCVT): Ditto.
+ (XANDESVBFHCVT): Ditto.
+ (XANDESVSINTLOAD): Ditto.
+ (XANDESVPACKFPH): Ditto.
+ (XANDESVDOT): Ditto.
+ * config/riscv/t-riscv: Add riscv-ext-andes.def.
+ * doc/riscv-ext.texi: Regenerated.
+ * config/riscv/riscv-ext-andes.def: New file.
+
+2025-09-03 Paul-Antoine Arras <parras@baylibre.com>
+
+ * config/riscv/autovec-opt.md (*vfmax_vf_<mode>): Rename into...
+ (*vf<optab>_vf_<mode>): New pattern to combine vec_duplicate +
+ vf{min,max}.vv into vf{max,min}.vf.
+ * J: New file.
+
+2025-09-03 Austin Law <austinklaw@gmail.com>
+
+ PR target/121213
+ * config/riscv/sync.md (amo_atomic_exchange_extended<mode>):
+ Separate insn with sign extension for 64 bit targets.
+
+2025-09-03 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-profile.cc (ipa_profile): Dump profile_info.
+
+2025-09-03 Jan Hubicka <hubicka@ucw.cz>
+
+ * opts.cc (enable_fdo_optimizations): Do not auto-enabele loop
+ optimizations with AutoFDO.
+
+2025-09-03 Jan Hubicka <hubicka@ucw.cz>
+
+ * params.opt (-param=lto-partitions=): INcrease default value from 128 to 512.
+
+2025-09-03 Kyrylo Tkachov <ktkachov@nvidia.com>
+
+ PR target/121749
+ * config/aarch64/aarch64-simd.md (aarch64_<shrn_op>shrn_n<mode>):
+ Use aarch64_simd_shift_imm_offset_<vn_mode> instead of
+ aarch64_simd_shift_imm_offset_<ve_mode> predicate.
+ (aarch64_<shrn_op>shrn_n<mode> VQN define_expand): Likewise.
+ (*aarch64_<shrn_op>rshrn_n<mode>_insn): Likewise.
+ (aarch64_<shrn_op>rshrn_n<mode>): Likewise.
+ (aarch64_<shrn_op>rshrn_n<mode> VQN define_expand): Likewise.
+ (aarch64_sqshrun_n<mode>_insn): Likewise.
+ (aarch64_sqshrun_n<mode>): Likewise.
+ (aarch64_sqshrun_n<mode> VQN define_expand): Likewise.
+ (aarch64_sqrshrun_n<mode>_insn): Likewise.
+ (aarch64_sqrshrun_n<mode>): Likewise.
+ (aarch64_sqrshrun_n<mode>): Likewise.
+ * config/aarch64/iterators.md (vn_mode): Handle DI, SI, HI modes.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/121756
+ * tree-ssa-sink.cc (select_best_block): Avoid irreducible
+ regions in otherwise same loop depth.
+ (statement_sink_location): When sinking a VDEF, never place
+ that into an irreducible region.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-patterns.cc (vect_recog_cond_expr_convert_pattern):
+ Do not set any vector types.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/121767
+ * tree-vect-patterns.cc (vect_recog_mod_var_pattern): Disable
+ for reductions.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/121758
+ * tree-vect-patterns.cc (vect_mark_pattern_stmts): Try
+ harder to find a reduction continuation.
+
+2025-09-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
+
+ PR tree-optimization/121355
+ * fold-const.cc (split_address_to_core_and_offset): Handle an MEM_REF after the call
+ to get_inner_reference.
+
2025-09-02 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
* tree-ssa-ccp.cc (optimize_memcmp_eq): New function.
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 18f16c3b1048..afd7c0026872 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250903
+20250904
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 082ce99b64c7..589737c6e4b7 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2025-09-03 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/97740
+ * pt.cc (tsubst_expr) <case COMPONENT_REF>: Don't check access
+ when the given member is already a FIELD_DECL.
+
2025-09-02 Iain Sandoe <iain@sandoe.co.uk>
* constexpr.cc: Include contracts.h
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 08cc5dc47942..ca02c378a704 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,10 @@
+2025-09-03 Harald Anlauf <anlauf@gmx.de>
+
+ PR fortran/121263
+ * trans-intrinsic.cc (gfc_conv_intrinsic_transfer): For an
+ unlimited polymorphic SOURCE to TRANSFER use saved descriptor
+ if possible.
+
2025-09-02 Paul Thomas <pault@gcc.gnu.org>
PR fortran/89707
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a447ea130458..6cbe4430f1ca 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,105 @@
+2025-09-03 Kuan-Lin Chen <rufus@andestech.com>
+
+ * gcc.target/riscv/xandes/xandesbfhcvt-1.c: New test.
+ * gcc.target/riscv/xandes/xandesbfhcvt-2.c: New test.
+
+2025-09-03 Kuan-Lin Chen <rufus@andestech.com>
+
+ * gcc.target/riscv/riscv.exp: Add runtest for subdir xandes.
+ * gcc.target/riscv/xandes/xandesperf-1.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-10.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-2.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-3.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-4.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-5.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-6.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-7.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-8.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-9.c: New test.
+ * gcc.target/riscv/xandes/xandesperf-11.c: New file.
+
+2025-09-03 Kuan-Lin Chen <rufus@andestech.com>
+
+ * gcc.target/riscv/xandes/xandes-predef-1.c: New test.
+ * gcc.target/riscv/xandes/xandes-predef-2.c: New test.
+ * gcc.target/riscv/xandes/xandes-predef-3.c: New test.
+ * gcc.target/riscv/xandes/xandes-predef-4.c: New test.
+ * gcc.target/riscv/xandes/xandes-predef-5.c: New test.
+ * gcc.target/riscv/xandes/xandes-predef-6.c: New test.
+ Co-author: Lino Hsing-Yu Peng (linopeng@andestech.com)
+ Co-author: Kai Kai-Yi Weng (kaiweng@andestech.com).
+
+2025-09-03 Paul-Antoine Arras <parras@baylibre.com>
+
+ * gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: Adjust scan
+ dump.
+ * gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmax. Also add
+ missing scan-dump for vfmul.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Add vfmax.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add max functions.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
+ vfmax.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f16.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f32.c: New test.
+ * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f64.c: New test.
+
+2025-09-03 Harald Anlauf <anlauf@gmx.de>
+
+ PR fortran/121263
+ * gfortran.dg/transfer_class_5.f90: New test.
+
+2025-09-03 Austin Law <austinklaw@gmail.com>
+
+ PR target/121213
+ * gcc.target/riscv/amo/pr121213.c: Remove xfail.
+
+2025-09-03 Kyrylo Tkachov <ktkachov@nvidia.com>
+
+ PR target/121749
+ * gcc.target/aarch64/simd/pr121749.c: Use dg-assemble directive.
+
+2025-09-03 Kyrylo Tkachov <ktkachov@nvidia.com>
+
+ PR target/121749
+ * gcc.target/aarch64/simd/pr121749.c: New test.
+
+2025-09-03 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/97740
+ * g++.dg/cpp0x/constexpr-97740a.C: New test.
+ * g++.dg/cpp0x/constexpr-97740b.C: New test.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/121756
+ * gcc.dg/torture/pr121756.c: New testcase.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/121767
+ * gcc.dg/vect/pr121767.c: New testcase.
+
+2025-09-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/121758
+ * gcc.dg/vect/pr121758.c: New testcase.
+
+2025-09-03 Andrew Pinski <andrew.pinski@oss.qualcomm.com>
+
+ PR tree-optimization/121355
+ * gcc.dg/tree-ssa/ptrdiff-1.c: New test.
+
2025-09-02 Paul Thomas <pault@gcc.gnu.org>
PR fortran/89707
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 7bc63862126e..c3119e02c3da 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,33 @@
+2025-09-03 Yihan Wang <yronglin777@gmail.com>
+
+ * include/std/expected (expected(U&&)): Add missing constraint
+ as per LWG 4222.
+ * testsuite/20_util/expected/lwg4222.cc: New test.
+
+2025-09-03 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/121745
+ * include/bits/stl_pair.h (get): Use forward instead of move in
+ std::get<T> overloads for rvalue pairs.
+ * testsuite/20_util/pair/astuple/get_by_type.cc: Check all value
+ categories and cv-qualification.
+
+2025-09-03 Jonathan Wakely <jwakely@redhat.com>
+
+ PR libstdc++/110853
+ * include/bits/stl_pair.h [C++20] (pair(const T1&, const T2&)):
+ Use std::type_identity_t<T1> for first parameter.
+ * testsuite/20_util/pair/cons/110853.cc: New test.
+
+2025-09-03 Jonathan Wakely <jwakely@redhat.com>
+
+ * include/bits/version.def (chrono_cxx20): Define.
+ * include/bits/version.h: Regenerate.
+ * include/std/chrono: Check __glibcxx_chrono_cxx20 instead of
+ __cpp_lib_chrono for C++20 features that don't require the new
+ std::string ABI and/or can be used for freestanding.
+ * src/c++20/clock.cc: Adjust preprocessor condition.
+
2025-09-02 Luc Grosheintz <luc.grosheintz@gmail.com>
* include/bits/utility.h (_Index_tuple): Move to <type_traits>.
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