[gcc r14-11579] Daily bump.
GCC Administrator
gccadmin@gcc.gnu.org
Thu Apr 10 00:22:47 GMT 2025
https://gcc.gnu.org/g:8406aec4ff09c55d521d6b0ac43b8ba43c68375a
commit r14-11579-g8406aec4ff09c55d521d6b0ac43b8ba43c68375a
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Thu Apr 10 00:22:21 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 232 ++++++++++++++++++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cp/ChangeLog | 7 ++
gcc/testsuite/ChangeLog | 146 ++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 13 +++
5 files changed, 399 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f088fad113f3..9b4379055d3f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,235 @@
+2025-04-09 Patrick O'Neill <patrick@rivosinc.com>
+
+ * config/riscv/riscv-v.cc (expand_const_vector): Fix STEP size in
+ expander.
+
+2025-04-09 xuli <xuli1@eswincomputing.com>
+
+ PR target/117286
+ * config/riscv/riscv-vector-builtins-bases.cc: Do not expand NULL return.
+
+2025-04-09 xuli <xuli1@eswincomputing.com>
+
+ PR target/117483
+ * config/riscv/riscv-vsetvl.cc: Fix bug.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ * config/riscv/riscv.cc (riscv_move_integer): Initialize "x".
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/116036
+ * config/riscv/riscv.cc (riscv_override_options_internal): Error
+ with TARGET_VECTOR && !TARGET_MUL.
+
+2025-04-09 Patrick O'Neill <patrick@rivosinc.com>
+
+ PR target/116111
+ * config/riscv/riscv.cc (riscv_option_override): Add error.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/116149
+ * config/riscv/vector.md: Fix mode_idx attribute of scalar
+ widen add/sub variants.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/116240
+ * config/riscv/riscv.cc (riscv_rtx_costs): Ensure object is a
+ comparison before looking at its arguments.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ * config/riscv/riscv.h (RISCV_DWARF_VLENB): Delete.
+
+2025-04-09 曾治金 <zhijin.zeng@spacemit.com>
+
+ PR target/116305
+ * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value): Take
+ BYTES_PER_RISCV_VECTOR for *factor instead of riscv_bytes_per_vector_chunk.
+
+2025-04-09 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/vector.md (mode_idx): Add vrol and vror.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/116086
+ * config/riscv/autovec.md (vec_extract<mode><v_half>): Add
+ vector-vector extract for VLS modes.
+ * config/riscv/riscv.cc (riscv_can_change_mode_class): Forbid
+ VLS modes larger than one vector.
+ * config/riscv/vector-iterators.md: Add vector-vector extract
+ iterators.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ PR target/116592
+ * config/riscv/thead.cc (th_asm_output_opcode): Change '0' to
+ "zero"
+
+2025-04-09 garthlei <garthlei@linux.alibaba.com>
+
+ * config/riscv/riscv-vsetvl.cc: Use `dest_vl` for dest VL operand
+
+2025-04-09 Andreas Schwab <schwab@suse.de>
+
+ PR target/116693
+ * config/riscv/riscv.cc (riscv_legitimize_tls_address): Don't pass
+ seqno to gen_tlsdesc and remove it.
+ * config/riscv/riscv.md (@tlsdesc<mode>): Remove operand 1. Use
+ %= instead of %1 in template.
+
+2025-04-09 Bohan Lei <garthlei@linux.alibaba.com>
+
+ * config/riscv/vector.md: Allow zero operand for DI variants of
+ vssubu.vx
+
+2025-04-09 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+
+ * config/riscv/thead.md (*th_extu<mode>4): Fix th.extu
+ operands exceeding range on rv32.
+
+2025-04-09 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+
+ * config/riscv/riscv.cc (riscv_rtx_costs): Fix the outer_code
+ when calculating the cost of SET expression.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/117544
+ * config/riscv/vector.md (*mov<mode>_whole): Split.
+ (*mov<mode>_fract): Ditto.
+ (*mov<mode>): Ditto.
+ (*mov<mode>_vls): Ditto.
+ (*mov<mode>_reg_whole_vtype): New pattern with vtype use.
+ (*mov<mode>_fract_vtype): Ditto.
+ (*mov<mode>_vtype): Ditto.
+ (*mov<mode>_vls_vtype): Ditto.
+
+2025-04-09 Pan Li <pan2.li@intel.com>
+
+ PR target/117878
+ * config/riscv/riscv-v.cc (vlmax_avl_type_p): Add assert for
+ out of range access.
+ (nonvlmax_avl_type_p): Ditto.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/117383
+ * config/riscv/riscv-protos.h (enum insn_type): Use TU policy.
+ * config/riscv/riscv-v.cc (shuffle_compress_patterns): Set VL.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/106544
+ * config/riscv/riscv.cc (riscv_print_operand): Issue an error for
+ invalid operands rather than invalidly accessing INTVAL of an
+ object that is not a CONST_INT. Fix one error string for 'N'.
+
+2025-04-09 Andreas Schwab <schwab@suse.de>
+
+ PR target/118137
+ * config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
+ to shifted value.
+
+2025-04-09 Robin Dapp <rdapp.gcc@gmail.com>
+
+ PR target/117682
+ * config/riscv/riscv-v.cc (expand_const_vector): Fall back to
+ merging if either step is negative.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/118154
+ * config/riscv/riscv-vsetvl.cc (MAX_LMUL): New define.
+ (pre_vsetvl::earliest_fuse_vsetvl_info): Use.
+ (pre_vsetvl::pre_global_vsetvl_info): New predicate with equal
+ ratio.
+ * config/riscv/riscv-vsetvl.def: Use.
+
+2025-04-09 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/118182
+ * config/riscv/autovec-opt.md (*widen_reduc_plus_scal_<mode>): Adjust
+ argument for expand_reduction.
+ (*widen_reduc_plus_scal_<mode>): Ditto.
+ (*fold_left_widen_plus_<mode>): Ditto.
+ (*mask_len_fold_left_widen_plus_<mode>): Ditto.
+ (*cond_widen_reduc_plus_scal_<mode>): Ditto.
+ (*cond_len_widen_reduc_plus_scal_<mode>): Ditto.
+ (*cond_widen_reduc_plus_scal_<mode>): Ditto.
+ * config/riscv/autovec.md (reduc_plus_scal_<mode>): Adjust argument for
+ expand_reduction.
+ (reduc_smax_scal_<mode>): Ditto.
+ (reduc_umax_scal_<mode>): Ditto.
+ (reduc_smin_scal_<mode>): Ditto.
+ (reduc_umin_scal_<mode>): Ditto.
+ (reduc_and_scal_<mode>): Ditto.
+ (reduc_ior_scal_<mode>): Ditto.
+ (reduc_xor_scal_<mode>): Ditto.
+ (reduc_plus_scal_<mode>): Ditto.
+ (reduc_smax_scal_<mode>): Ditto.
+ (reduc_smin_scal_<mode>): Ditto.
+ (reduc_fmax_scal_<mode>): Ditto.
+ (reduc_fmin_scal_<mode>): Ditto.
+ (fold_left_plus_<mode>): Ditto.
+ (mask_len_fold_left_plus_<mode>): Ditto.
+ * config/riscv/riscv-v.cc (expand_reduction): Add one more
+ argument for reduction code for vl0-safe.
+ * config/riscv/riscv-protos.h (expand_reduction): Ditto.
+ * config/riscv/vector-iterators.md (unspec): Add _VL0_SAFE variant of
+ reduction.
+ (ANY_REDUC_VL0_SAFE): New.
+ (ANY_WREDUC_VL0_SAFE): Ditto.
+ (ANY_FREDUC_VL0_SAFE): Ditto.
+ (ANY_FREDUC_SUM_VL0_SAFE): Ditto.
+ (ANY_FWREDUC_SUM_VL0_SAFE): Ditto.
+ (reduc_op): Add _VL0_SAFE variant of reduction.
+ (order) Ditto.
+ * config/riscv/vector.md (@pred_<reduc_op><mode>): New.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ PR target/118357
+ * config/riscv/riscv-vsetvl.cc: Function change_vtype_only_p always
+ returns false for XTheadVector.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/116308
+ * config/riscv/riscv.cc (riscv_lshift_subword): Use gen_lowpart
+ rather than simplify_gen_subreg.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/116256
+ * config/riscv/predicates.md (consecutive_bits_operand): Properly
+ handle (const_int 0).
+
+2025-04-09 Yang Yujie <yangyujie@loongson.cn>
+
+ Backported from master:
+ 2025-04-09 Yang Yujie <yangyujie@loongson.cn>
+
+ * config/loongarch/genopts/gen-evolution.awk: remove
+ usage of "asort".
+ * config/loongarch/genopts/genstr.sh: replace sed with awk.
+
+2025-04-09 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2025-04-03 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/genopts/gen-evolution.awk: Avoid using gensub
+ that FreeBSD awk lacks.
+
2025-04-02 Richard Biener <rguenther@suse.de>
Backported from master:
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index cb38c2c30be3..4013552f78d6 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250409
+20250410
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 3021c2f062c2..9620aabeeb4d 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,10 @@
+2025-04-09 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/119574
+ * pt.cc (tsubst_lambda_expr): Don't call
+ get_innermost_template_args if we're requesting too many
+ levels.
+
2025-04-07 Jason Merrill <jason@redhat.com>
Backported from master:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index cde16d56a352..0fb09845abb5 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,149 @@
+2025-04-09 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/119574
+ * g++.dg/cpp2a/lambda-targ13.C: New test.
+ * g++.dg/cpp2a/lambda-targ13a.C: New test.
+
+2025-04-09 xuli <xuli1@eswincomputing.com>
+
+ PR target/117286
+ * gcc.target/riscv/rvv/base/pr117286.c: New test.
+
+2025-04-09 xuli <xuli1@eswincomputing.com>
+
+ PR target/117483
+ * gcc.target/riscv/pr117483.c: New test.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/arch-31.c: Add m to arch string and expect it.
+ * gcc.target/riscv/arch-32.c: Ditto.
+ * gcc.target/riscv/predef-14.c: Ditto.
+ * gcc.target/riscv/predef-15.c: Ditto.
+ * gcc.target/riscv/predef-16.c: Ditto.
+ * gcc.target/riscv/predef-26.c: Ditto.
+ * gcc.target/riscv/predef-27.c: Ditto.
+ * gcc.target/riscv/predef-32.c: Ditto.
+ * gcc.target/riscv/predef-33.c: Ditto.
+ * gcc.target/riscv/rvv/autovec/pr111486.c: Add m to arch string.
+ * gcc.target/riscv/compare-debug-1.c: Ditto.
+ * gcc.target/riscv/compare-debug-2.c: Ditto.
+ * gcc.target/riscv/rvv/base/pr116036.c: New test.
+
+2025-04-09 Patrick O'Neill <patrick@rivosinc.com>
+
+ * gcc.target/riscv/arch-41.c: New test.
+ * gcc.target/riscv/pr116111.c: New test.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/pr116149.c: New test.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/116240
+ * gcc.target/riscv/pr116240.c: New test.
+
+2025-04-09 曾治金 <zhijin.zeng@spacemit.com>
+
+ PR target/116305
+ * gcc.target/riscv/rvv/base/scalable_vector_cfi.c: New test.
+
+2025-04-09 Kito Cheng <kito.cheng@sifive.com>
+
+ * gcc.target/riscv/rvv/autovec/rotr.c: New.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/116086
+ * lib/target-supports.exp: Add effective target checks for
+ zvl256b and zvl512b.
+ * gcc.target/riscv/rvv/autovec/pr116086-2-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/pr116086-2.c: New test.
+ * gcc.target/riscv/rvv/autovec/pr116086.c: New test.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ PR target/116592
+ * gcc.target/riscv/rvv/xtheadvector/pr116592.c: New test.
+
+2025-04-09 garthlei <garthlei@linux.alibaba.com>
+
+ * gcc.target/riscv/rvv/vsetvl/vsetvl_bug-3.c: New test.
+
+2025-04-09 Bohan Lei <garthlei@linux.alibaba.com>
+
+ * gcc.target/riscv/rvv/base/vssubu-1.c: New test.
+ * gcc.target/riscv/rvv/base/vssubu-2.c: New test.
+
+2025-04-09 Xianmiao Qu <cooper.qu@linux.alibaba.com>
+
+ * gcc.target/riscv/xtheadbb-extu-4.c: New.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/117544
+ * gcc.target/riscv/rvv/base/abi-call-args-4.c: Expect vsetvl.
+ * gcc.target/riscv/rvv/base/pr117544.c: New test.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/117383
+ * gcc.target/riscv/rvv/autovec/binop/vcompress-avlprop-1.c:
+ Expect tu.
+ * gcc.target/riscv/rvv/autovec/pr117383.c: New test.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/106544
+ * gcc.target/riscv/pr106544.c: New test.
+
+2025-04-09 Andreas Schwab <schwab@suse.de>
+
+ PR target/118137
+ * gcc.dg/atomic/pr118137.c: New.
+
+2025-04-09 Robin Dapp <rdapp.gcc@gmail.com>
+
+ PR target/117682
+ * gcc.target/riscv/rvv/autovec/pr117682.c: New test.
+
+2025-04-09 Robin Dapp <rdapp@ventanamicro.com>
+
+ PR target/118154
+ * gcc.target/riscv/rvv/autovec/pr118154-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/pr118154-2.c: New test.
+
+2025-04-09 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/118182
+ * gfortran.target/riscv/rvv/pr118182.f: New.
+ * gcc.target/riscv/rvv/autovec/pr118182-1.c: New.
+ * gcc.target/riscv/rvv/autovec/pr118182-2.c: New.
+
+2025-04-09 Kito Cheng <kito.cheng@sifive.com>
+
+ * gcc.target/riscv/rvv/fortran/pr111395.f90: Move this file to...
+ * gfortran.target/riscv/rvv/pr111395.f90: ...here.
+ * gcc.target/riscv/rvv/fortran/pr111566.f90: Move this file to...
+ * gfortran.target/riscv/rvv/pr111566.f90: ...here.
+ * gcc.target/riscv/rvv/rvv-fortran.exp: Move this file to...
+ * gfortran.target/riscv/rvv/rvv.exp: ...here.
+
+2025-04-09 Jin Ma <jinma@linux.alibaba.com>
+
+ PR target/118357
+ * gcc.target/riscv/rvv/xtheadvector/pr118357.c: New test.
+
+2025-04-09 Jeff Law <jlaw@ventanamicro.com>
+
+ PR target/116308
+ * gcc.target/riscv/pr116308.c: New test.
+
2025-04-07 Jason Merrill <jason@redhat.com>
Backported from master:
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 56e4f0421781..48bdcdb2156e 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,16 @@
+2025-04-09 Patrick Palka <ppalka@redhat.com>
+
+ Backported from master:
+ 2025-04-09 Patrick Palka <ppalka@redhat.com>
+
+ PR libstdc++/115046
+ PR libstdc++/112490
+ * include/bits/stl_iterator.h (basic_const_iterator::operator-):
+ Replace non-dependent basic_const_iterator function parameter with
+ a dependent one of type basic_const_iterator<_It2> where _It2
+ matches _It.
+ * testsuite/std/ranges/adaptors/as_const/1.cc (test04): New test.
+
2025-04-08 Jonathan Wakely <jwakely@redhat.com>
Backported from master:
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