[gcc r15-7170] Daily bump.
GCC Administrator
gccadmin@gcc.gnu.org
Fri Jan 24 00:19:25 GMT 2025
https://gcc.gnu.org/g:35d5c4f9f479afa3ee585b617cc73a03d44297f4
commit r15-7170-g35d5c4f9f479afa3ee585b617cc73a03d44297f4
Author: GCC Administrator <gccadmin@gcc.gnu.org>
Date: Fri Jan 24 00:18:58 2025 +0000
Daily bump.
Diff:
---
gcc/ChangeLog | 349 +++++++++++++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/c-family/ChangeLog | 10 +
gcc/c/ChangeLog | 6 +
gcc/cp/ChangeLog | 43 +++++
gcc/fortran/ChangeLog | 19 ++
gcc/testsuite/ChangeLog | 503 ++++++++++++++++++++++++++++++++++++++++++++++++
libstdc++-v3/ChangeLog | 6 +
8 files changed, 937 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e7385ea9a3e..4665edc25598 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,352 @@
+2025-01-23 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
+ register 86 name to "%fr31L".
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/118628
+ * tree-vect-stmts.cc (vectorizable_store, vectorizable_load):
+ Initialize offvar to NULL_TREE.
+
+2025-01-23 Georg-Johann Lay <avr@gjlay.de>
+
+ PR tree-optimization/118012
+ PR tree-optimization/118360
+ * config/avr/avr.opt (-mpr118012): New undocumented option.
+ * config/avr/avr-protos.h (avr_out_sextr)
+ (avr_emit_skip_pixop, avr_emit_skip_clear): New protos.
+ * config/avr/avr.cc (avr_adjust_insn_length)
+ [case ADJUST_LEN_SEXTR]: Handle case.
+ (avr_rtx_costs_1) [NEG]: Costs for NEG (ZERO_EXTEND (ZERO_EXTRACT)).
+ [MULT && avropt_pr118012]: Costs for MULT (x AND 1).
+ (avr_out_sextr, avr_emit_skip_pixop, avr_emit_skip_clear): New
+ functions.
+ * config/avr/avr.md [avropt_pr118012]: Add combine patterns with
+ that condition that try to work around PR118012.
+ (adjust_len) <sextr>: Add insn attr value.
+ (pixop): New code iterator.
+ (mulsi3) [avropt_pr118012 && !AVR_TINY]: Allow these in insn condition.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR rtl-optimization/118562
+ * rtl-ssa/blocks.cc (function_info::replace_phi): When converting
+ to a degenerate phi, make sure to remove all uses of the previous
+ inputs.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64-tuning-flags.def
+ (AARCH64_EXTRA_TUNE_CHEAP_FPMR_WRITE): New tuning flag.
+ * config/aarch64/aarch64.h (TARGET_CHEAP_FPMR_WRITE): New macro.
+ * config/aarch64/aarch64.md: Split moves into FPMR into a test
+ and branch around.
+ (aarch64_write_fpmr): New pattern.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.cc (aarch64_memory_move_cost): Account
+ for the cost of moving in and out of GENERAL_SYSREGS.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64)
+ (*movsi_aarch64, *movdi_aarch64): Allow the source of an MSR
+ to be zero.
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/118605
+ * tree-assume.cc (assume_query::m_parm_list): Change type
+ from bitmap & to bitmap.
+
+2025-01-23 Tejas Belagod <tejas.belagod@arm.com>
+
+ * omp-low.cc (use_pointer_for_field): Use pointer if the OMP data
+ structure's field type is a poly-int.
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114877
+ * builtins.cc (fold_builtin_frexp): Handle rvc_nan and rvc_inf cases
+ like rvc_zero, return passed in arg and set *exp = 0.
+
+2025-01-23 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
+
+ * doc/sourcebuild.texi (Effective-Target Keywords): Document
+ 'alarm'.
+
+2025-01-23 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/117726
+ * config/avr/avr.cc (avr_ld_regno_p): New function.
+ (ashlsi3_out) [case 25,26,27,28,29,30]: Handle and tweak.
+ (lshrsi3_out): Same.
+ (avr_rtx_costs_1) [SImode, ASHIFT, LSHIFTRT]: Adjust costs.
+ * config/avr/avr.md (ashlsi3, *ashlsi3, *ashlsi3_const):
+ Add "r,r,C4L" alternative.
+ (lshrsi3, *lshrsi3, *lshrsi3_const): Add "r,r,C4R" alternative.
+ * config/avr/constraints.md (C4R, C4L): New,
+
+2025-01-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/118558
+ * tree-vectorizer.h (vect_known_alignment_in_bytes): Pass
+ through offset to dr_misalignment.
+ * tree-vect-stmts.cc (get_group_load_store_type): Compute
+ offset applied for negative stride and use it when querying
+ alignment of accesses.
+ (vectorizable_load): Likewise.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/107741
+ * common.opt: Add -fabi-version=20.
+ * doc/invoke.texi: Likewise.
+
+2025-01-23 Xi Ruoyao <xry111@xry111.site>
+
+ PR target/118501
+ * config/loongarch/loongarch.md (@xorsign<mode>3): Use
+ force_lowpart_subreg.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ * config/i386/avx10_2-512convertintrin.h:
+ Omit "p" for packed for FP8.
+ * config/i386/avx10_2convertintrin.h: Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512satcvtintrin.h: Change intrin and
+ builtin name according to new mnemonics.
+ * config/i386/avx10_2satcvtintrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_VCVTBF162IBS): Rename from UNSPEC_VCVTNEBF162IBS.
+ (UNSPEC_VCVTBF162IUBS): Rename from UNSPEC_VCVTNEBF162IUBS.
+ (UNSPEC_VCVTTBF162IBS): Rename from UNSPEC_VCVTTNEBF162IBS.
+ (UNSPEC_VCVTTBF162IUBS): Rename from UNSPEC_VCVTTNEBF162IUBS.
+ (UNSPEC_CVTNE_BF16_IBS_ITER): Rename to...
+ (UNSPEC_CVT_BF16_IBS_ITER): ...this. Adjust UNSPEC name.
+ (sat_cvt_sign_prefix): Adjust UNSPEC name.
+ (sat_cvt_trunc_prefix): Ditto.
+ (avx10_2_cvt<sat_cvt_trunc_prefix>nebf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
+ Rename to...
+ (avx10_2_cvt<sat_cvt_trunc_prefix>bf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
+ ...this. Change instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512convertintrin.h: Change intrin and
+ builtin name according to new mnemonics.
+ * config/i386/avx10_2convertintrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_VCVTPH2BF8): Rename from UNSPEC_VCVTNEPH2BF8.
+ (UNSPEC_VCVTPH2BF8S): Rename from UNSPEC_VCVTNEPH2BF8S.
+ (UNSPEC_VCVTPH2HF8): Rename from UNSPEC_VCVTNEPH2HF8.
+ (UNSPEC_VCVTPH2HF8S): Rename from UNSPEC_VCVTNEPH2HF8S.
+ (UNSPEC_CONVERTPH2FP8): Rename from UNSPEC_NECONVERTPH2FP8.
+ Adjust UNSPEC name.
+ (convertph2fp8): Rename from neconvertph2fp8. Adjust
+ iterator map.
+ (vcvt<neconvertph2fp8>v8hf): Rename to...
+ (vcvt<neconvertph2fp8>v8hf): ...this.
+ (*vcvt<neconvertph2fp8>v8hf): Rename to...
+ (*vcvt<neconvertph2fp8>v8hf): ...this.
+ (vcvt<neconvertph2fp8>v8hf_mask): Rename to...
+ (vcvt<neconvertph2fp8>v8hf_mask): ...this.
+ (*vcvt<neconvertph2fp8>v8hf_mask): Rename to...
+ (*vcvt<neconvertph2fp8>v8hf_mask): ...this.
+ (vcvt<neconvertph2fp8><mode><mask_name>): Rename to...
+ (vcvt<convertph2fp8><mode><mask_name>): ...this.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512convertintrin.h: Change intrin and
+ builtin name according to new mnemonics.
+ * config/i386/avx10_2convertintrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_VCVT2PH2BF8): Rename from UNSPEC_VCVTNE2PH2BF8.
+ (UNSPEC_VCVT2PH2BF8S): Rename from UNSPEC_VCVTNE2PH2BF8S.
+ (UNSPEC_VCVT2PH2HF8): Rename from UNSPEC_VCVTNE2PH2HF8.
+ (UNSPEC_VCVT2PH2HF8S): Rename from UNSPEC_VCVTNE2PH2HF8S.
+ (UNSPEC_CONVERTFP8_PACK): Rename from UNSPEC_NECONVERTFP8_PACK.
+ Adjust UNSPEC name.
+ (convertfp8_pack): Rename from neconvertfp8_pack. Adjust
+ iterator map.
+ (vcvt<neconvertfp8_pack><mode><mask_name>): Rename to...
+ (vcvt<convertfp8_pack><mode><mask_name>): ...this.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2bf16intrin.h: Change intrin and builtin
+ name according to new mnemonics.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/i386-expand.cc
+ (ix86_expand_fp_compare): Adjust comments.
+ (ix86_expand_builtin): Adjust switch case.
+ * config/i386/i386.md (cmpibf): Change instruction name output.
+ * config/i386/sse.md (UNSPEC_VCOMSBF16): Removed.
+ (avx10_2_comisbf16_v8bf): New.
+ (avx10_2_comsbf16_v8bf): Removed.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
+ name according to new mnemonics.
+ * config/i386/avx10_2bf16intrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_VFPCLASSBF16); Rename from UNSPEC_VFPCLASSPBF16.
+ (avx10_2_getexppbf16_<mode><mask_name>): Rename to...
+ (avx10_2_getexpbf16_<mode><mask_name>): ...this.
+ Change instruction name output.
+ (avx10_2_fpclasspbf16_<mode><mask_scalar_merge_name>):
+ Rename to...
+ (avx10_2_fpclassbf16_<mode><mask_scalar_merge_name>): ...this.
+ Change instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
+ name according to new mnemonics.
+ * config/i386/avx10_2bf16intrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_VSCALEFBF16): Rename from UNSPEC_VSCALEFPBF16.
+ (avx10_2_scalefpbf16_<mode><mask_name>): Rename to...
+ (avx10_2_scalefbf16_<mode><mask_name>): ...this.
+ Change instruction name output.
+ (avx10_2_rsqrtpbf16_<mode><mask_name>): Rename to...
+ (avx10_2_rsqrtbf16_<mode><mask_name>): ...this.
+ Change instruction name output.
+ (avx10_2_sqrtnepbf16_<mode><mask_name>): Rename to...
+ (avx10_2_sqrtbf16_<mode><mask_name>): ...this.
+ Change instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
+ name according to new mnemonics.
+ * config/i386/avx10_2bf16intrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_VRNDSCALEBF16): Rename from UNSPEC_VRNDSCALENEPBF16.
+ (UNSPEC_VREDUCEBF16): Rename from UNSPEC_VREDUCENEPBF16.
+ (UNSPEC_VGETMANTBF16): Rename from UNSPEC_VGETMANTPBF16.
+ (BF16IMMOP): Adjust iterator due to UNSPEC name change.
+ (bf16immop): Ditto.
+ (avx10_2_<bf16immop>pbf16_<mode><mask_name>): Rename to...
+ (avx10_2_<bf16immop>bf16_<mode><mask_name>): ...this. Change
+ instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512minmaxintrin.h: Change intrin and
+ builtin name according to new mnemonics.
+ * config/i386/avx10_2minmaxintrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (UNSPEC_MINMAXBF16): Rename from UNSPEC_MINMAXNEPBF16.
+ (avx10_2_minmaxnepbf16_<mode><mask_name>): Rename to...
+ (avx10_2_minmaxbf16_<mode><mask_name>): ...this. Change
+ instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
+ name according to new mnemonics.
+ * config/i386/avx10_2bf16intrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (avx10_2_<code>pbf16_<mode><mask_name>): Rename to...
+ (avx10_2_<code>bf16_<mode><mask_name>): ...this.
+ Change instruction name output.
+ (avx10_2_cmppbf16_<mode><mask_scalar_merge_name>): Rename to...
+ (avx10_2_cmpbf16_<mode><mask_scalar_merge_name>): ...this.
+ Change instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
+ names according to new mnemonics.
+ * config/i386/avx10_2bf16intrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md
+ (avx10_2_fmaddnepbf16_<mode>_maskz): Rename to...
+ (avx10_2_fmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
+ (avx10_2_fmaddnepbf16_<mode><sd_maskz_name>): Rename to...
+ (avx10_2_fmaddbf16_<mode><sd_maskz_name>): ...this.
+ Change instruction name output.
+ (avx10_2_fmaddnepbf16_<mode>_mask): Rename to...
+ (avx10_2_fmaddbf16_<mode>_mask): ...this.
+ Change instruction name output.
+ (avx10_2_fmaddnepbf16_<mode>_mask3): Rename to...
+ (avx10_2_fmaddbf16_<mode>_mask3): ...this.
+ Change instruction name output.
+ (avx10_2_fnmaddnepbf16_<mode>_maskz): Rename to...
+ (avx10_2_fnmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
+ (avx10_2_fnmaddnepbf16_<mode><sd_maskz_name>): Rename to...
+ (avx10_2_fnmaddbf16_<mode><sd_maskz_name>): ...this.
+ Change instruction name output.
+ (avx10_2_fnmaddnepbf16_<mode>_mask): Rename to...
+ (avx10_2_fnmaddbf16_<mode>_mask): ...this.
+ Change instruction name output.
+ (avx10_2_fnmaddnepbf16_<mode>_mask3): Rename to...
+ (avx10_2_fnmaddbf16_<mode>_mask3): ...this.
+ Change instruction name output.
+ (avx10_2_fmsubnepbf16_<mode>_maskz): Rename to...
+ (avx10_2_fmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
+ (avx10_2_fmsubnepbf16_<mode><sd_maskz_name>): Rename to...
+ (avx10_2_fmsubbf16_<mode><sd_maskz_name>): ...this.
+ Change instruction name output.
+ (avx10_2_fmsubnepbf16_<mode>_mask): Rename to...
+ (avx10_2_fmsubbf16_<mode>_mask): ...this.
+ Change instruction name output.
+ (avx10_2_fmsubnepbf16_<mode>_mask3): Rename to...
+ (avx10_2_fmsubbf16_<mode>_mask3): ...this.
+ Change instruction name output.
+ (avx10_2_fnmsubnepbf16_<mode>_maskz): Rename to...
+ (avx10_2_fnmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
+ (avx10_2_fnmsubnepbf16_<mode><sd_maskz_name>): Rename to...
+ (avx10_2_fnmsubbf16_<mode><sd_maskz_name>): ...this.
+ Change instruction name output.
+ (avx10_2_fnmsubnepbf16_<mode>_mask): Rename to...
+ (avx10_2_fnmsubbf16_<mode>_mask): ...this.
+ Change instruction name output.
+ (avx10_2_fnmsubnepbf16_<mode>_mask3): Rename to...
+ (avx10_2_fnmsubbf16_<mode>_mask3): ...this.
+ Change instruction name output.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
+ name according to new mnemonics.
+ * config/i386/avx10_2bf16intrin.h: Ditto.
+ * config/i386/i386-builtin.def (BDESC): Ditto.
+ * config/i386/sse.md (div<mode>3): Adjust emit_insn.
+ (avx10_2_<insn>nepbf16_<mode><mask_name>): Rename to...
+ (avx10_2_<insn>bf16_<mode><mask_name>): ...this. Change
+ instruction name output.
+ (avx10_2_rcppbf16_<mode><mask_name>): Rename to...
+ (avx10_2_rcpbf16_<mode><mask_name>):...this. Change
+ instruction name output.
+
2025-01-22 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
* config/s390/s390.cc: Fix arch15 machine string which must not
diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 3aae2a0a2efe..56a27e9356ca 100644
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20250123
+20250124
diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index fcb5bdcce2a6..c93531af9f05 100644
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,13 @@
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ * c-common.cc (make_tree_vector_from_ctor): Only use make_tree_vector
+ for ctors with <= 16 elements.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/107741
+ * c-opts.cc (c_common_post_options): Bump ABI version.
+
2025-01-22 Jakub Jelinek <jakub@redhat.com>
* c-common.h (append_ctor_to_tree_vector): Declare.
diff --git a/gcc/c/ChangeLog b/gcc/c/ChangeLog
index 7d81e07779d9..50b2b1fd26d0 100644
--- a/gcc/c/ChangeLog
+++ b/gcc/c/ChangeLog
@@ -1,3 +1,9 @@
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/118604
+ * c-parser.cc (c_parser_omp_metadirective): Rewrite
+ condition for clauses other than when, default and otherwise.
+
2025-01-21 Jakub Jelinek <jakub@redhat.com>
* c-decl.cc (names_builtin_p): Return 1 for RID_C23_VA_START and
diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index e8108354f04a..62cee4efc3a6 100644
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,46 @@
+2025-01-23 Marek Polacek <polacek@redhat.com>
+
+ PR c++/117602
+ * cp-tree.h (current_nonlambda_scope): Add a default argument.
+ * lambda.cc (current_nonlambda_scope): New bool parameter. Use it.
+ * parser.cc (cp_parser_lambda_introducer): Use current_nonlambda_scope
+ to check if the lambda is non-local.
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/118590
+ * typeck.cc (build_omp_array_section): If array_expr is type dependent
+ or a TYPE_DECL, build OMP_ARRAY_SECTION with NULL type.
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/118604
+ * parser.cc (cp_parser_omp_metadirective): Test !default_p
+ first and use strcmp () != 0 rather than !strcmp () == 0.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ * mangle.cc (write_expression): Update mangling for lambdas.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/107741
+ * cp-tree.h (start_initialized_static_member): Declare.
+ (finish_initialized_static_member): Declare.
+ * decl2.cc (start_initialized_static_member): New function.
+ (finish_initialized_static_member): New function.
+ * lambda.cc (record_lambda_scope): Support falling back to old
+ ABI (maybe with warning).
+ * parser.cc (cp_parser_member_declaration): Build decl early
+ when parsing an initialized static data member.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/118582
+ * module.cc (trees_out::decl_value): Always stream
+ imported_temploid_friends information.
+ (trees_in::decl_value): Likewise.
+
2025-01-22 Jakub Jelinek <jakub@redhat.com>
PR c++/115769
diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index d4fffec7ad2d..d7f660356f8b 100644
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,22 @@
+2025-01-23 Harald Anlauf <anlauf@gmx.de>
+
+ PR fortran/118613
+ * trans-intrinsic.cc (gfc_conv_intrinsic_minmaxval): Adjust algorithm
+ for inlined version of MINLOC and MAXLOC so that arguments are only
+ evaluted once, and create temporaries where necessary. Document
+ change of algorithm.
+
+2025-01-23 Paul Thomas <pault@gcc.gnu.org>
+
+ PR fortran/96087
+ * trans-decl.cc (gfc_get_symbol_decl): If a dummy is missing a
+ backend decl, it is likely that it has come from a module proc
+ interface. Look for the formal symbol by name in the containing
+ proc and use its backend decl.
+ * trans-expr.cc (gfc_apply_interface_mapping_to_expr): For the
+ same reason, match the name, rather than the symbol address to
+ perform the mapping.
+
2025-01-20 Harald Anlauf <anlauf@gmx.de>
PR fortran/107122
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 09b5300be7ad..f62e58c00112 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,506 @@
+2025-01-23 Marek Polacek <polacek@redhat.com>
+
+ PR c++/117602
+ * g++.dg/cpp2a/lambda-uneval21.C: New test.
+
+2025-01-23 Harald Anlauf <anlauf@gmx.de>
+
+ PR fortran/118613
+ * gfortran.dg/maxval_arg_eval_count.f90: New test.
+
+2025-01-23 Georg-Johann Lay <avr@gjlay.de>
+
+ PR tree-optimization/118012
+ PR tree-optimization/118360
+ * gcc.target/avr/mmcu/pr118012-1.h: New file.
+ * gcc.target/avr/mmcu/pr118012-1-o2-m128.c: New test.
+ * gcc.target/avr/mmcu/pr118012-1-os-m128.c: New test.
+ * gcc.target/avr/mmcu/pr118012-1-o2-m103.c: New test.
+ * gcc.target/avr/mmcu/pr118012-1-os-m103.c: New test.
+ * gcc.target/avr/mmcu/pr118012-1-o2-t40.c: New test.
+ * gcc.target/avr/mmcu/pr118012-1-os-t40.c: New test.
+ * gcc.target/avr/mmcu/pr118360-1.h: New file.
+ * gcc.target/avr/mmcu/pr118360-1-o2-m128.c: New test.
+ * gcc.target/avr/mmcu/pr118360-1-os-m128.c: New test.
+ * gcc.target/avr/mmcu/pr118360-1-o2-m103.c: New test.
+ * gcc.target/avr/mmcu/pr118360-1-os-m103.c: New test.
+ * gcc.target/avr/mmcu/pr118360-1-o2-t40.c: New test.
+ * gcc.target/avr/mmcu/pr118360-1-os-t40.c: New test.
+
+2025-01-23 Jan Hubicka <jh@suse.cz>
+
+ PR target/80813
+ * g++.dg/tree-ssa/bvector-3.C: New test.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR rtl-optimization/118562
+ * gcc.dg/torture/pr118562.c: New test.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Add
+ cheap_fpmr_write by default.
+ * gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Likewise.
+ * gcc.target/aarch64/acle/fp8.c: Add cheap_fpmr_write.
+ * gcc.target/aarch64/acle/fpmr-2.c: Likewise.
+ * gcc.target/aarch64/simd/vcvt_fpm.c: Likewise.
+ * gcc.target/aarch64/simd/vdot2_fpm.c: Likewise.
+ * gcc.target/aarch64/simd/vdot4_fpm.c: Likewise.
+ * gcc.target/aarch64/simd/vmla_fpm.c: Likewise.
+ * gcc.target/aarch64/acle/fpmr-6.c: New test.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gcc.target/aarch64/acle/fpmr-5.c: New test.
+ * gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c: Don't expect
+ a spill slot to be allocated.
+ * gcc.target/aarch64/sve2/acle/asm/mlalb_lane_mf8.c: Likewise.
+ * gcc.target/aarch64/sve2/acle/asm/mlallbb_lane_mf8.c: Likewise.
+ * gcc.target/aarch64/sve2/acle/asm/mlallbt_lane_mf8.c: Likewise.
+ * gcc.target/aarch64/sve2/acle/asm/mlalltb_lane_mf8.c: Likewise.
+ * gcc.target/aarch64/sve2/acle/asm/mlalltt_lane_mf8.c: Likewise.
+ * gcc.target/aarch64/sve2/acle/asm/mlalt_lane_mf8.c: Likewise.
+
+2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gcc.target/aarch64/acle/fp8.c: Add tests for moving zero into FPMR.
+
+2025-01-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ * gcc.target/i386/cmov12.c (scan-assembler-times): Allow for
+ cmovl.g etc.
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/118590
+ * g++.dg/goacc/pr118590.C: New test.
+
+2025-01-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/114877
+ * gcc.dg/torture/builtin-frexp-1.c: Add -Wmaybe-uninitialized as
+ dg-additional-options.
+ (bar): New function.
+ (TESTIT_FREXP2): Rework the macro so that it doesn't test whether
+ nothing has been stored to what the second argument points to, but
+ instead that something has been stored there, whatever it is.
+ (main): Temporarily don't enable the nan tests for -O0.
+
+2025-01-23 Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
+
+ * gcc.dg/pr78185.c: Remove dg-do and replace with
+ with dg-require-effective-target of signal and alarm.
+ * gcc.dg/pr116906-1.c: Likewise.
+ * gcc.dg/pr116906-2.c: Likewise.
+ * gcc.dg/vect/pr101145inf.c: Use effective-target alarm.
+ * gcc.dg/vect/pr101145inf_1.c: Likewise.
+ * lib/target-supports.exp(check_effective_target_alarm): New.
+
+2025-01-23 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/117726
+ * gcc.target/avr/torture/avr-torture.exp (AVR_TORTURE_OPTIONS):
+ Turn one option variant into -Oz.
+
+2025-01-23 Paul Thomas <pault@gcc.gnu.org>
+
+ PR fortran/96087
+ * gfortran.dg/pr96087.f90: New test.
+
+2025-01-23 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/118558
+ * gcc.dg/vect/pr118558.c: New testcase.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ * g++.dg/cpp2a/lambda-generic-mangle1.C: Update mangling.
+ * g++.dg/cpp2a/lambda-generic-mangle1a.C: Likewise.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/107741
+ * g++.dg/abi/macro0.C: Bump ABI version.
+ * g++.dg/abi/mangle74.C: Remove XFAILs.
+ * g++.dg/other/fold1.C: Restore originally raised error.
+ * g++.dg/abi/lambda-ctx2-19.C: New test.
+ * g++.dg/abi/lambda-ctx2-19vs20.C: New test.
+ * g++.dg/abi/lambda-ctx2-20.C: New test.
+ * g++.dg/abi/lambda-ctx2.h: New test.
+ * g++.dg/cpp0x/static-member-init-1.C: New test.
+
+2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
+
+ PR c++/118582
+ * g++.dg/modules/pr118582_a.H: New test.
+ * g++.dg/modules/pr118582_b.H: New test.
+ * g++.dg/modules/pr118582_c.H: New test.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ * gcc.target/i386/avx10_2-512-convert-1.c: Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtbiasph2bf8-2.c: Ditto.
+ * gcc.target/i386/avx10_2-512-vcvtbiasph2bf8s-2.c: Ditto.
+ * gcc.target/i386/avx10_2-512-vcvtbiasph2hf8-2.c: Ditto.
+ * gcc.target/i386/avx10_2-512-vcvtbiasph2hf8s-2.c: Ditto.
+ * gcc.target/i386/avx10_2-convert-1.c: Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-satcvt-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtnebf162ibs-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvtbf162ibs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtnebf162iubs-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvtbf162iubs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvttnebf162ibs-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvttbf162ibs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvttnebf162iubs-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvttbf162iubs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-satcvt-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-vcvtnebf162ibs-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvtbf162ibs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtnebf162iubs-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvtbf162iubs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvttnebf162ibs-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvttbf162ibs-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvttnebf162iubs-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvttbf162iubs-2.c: ...here.
+ Adjust intrin call.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-convert-1.c: Adjust output
+ and intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtneph2bf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvtph2bf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtneph2bf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvtph2bf8s-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtneph2hf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvtph2hf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtneph2hf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvtph2hf8s-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-convert-1.c: Adjust output
+ and intrin call.
+ * gcc.target/i386/avx10_2-vcvtneph2bf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvtph2bf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtneph2hf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvtph2bf8s-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtneph2bf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvtph2hf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtneph2hf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvtph2hf8s-2.c: ...here.
+ Adjust intrin call.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-convert-1.c: Adjust output
+ and intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtne2ph2bf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvt2ph2bf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtne2ph2bf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvt2ph2bf8s-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtne2ph2hf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvt2ph2hf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vcvtne2ph2hf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcvt2ph2hf8s-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-convert-1.c: Adjust output
+ and intrin call.
+ * gcc.target/i386/avx10_2-vcvtne2ph2bf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvt2ph2bf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtne2ph2hf8-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvt2ph2bf8s-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtne2ph2bf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvt2ph2hf8-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vcvtne2ph2hf8s-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcvt2ph2hf8s-2.c: ...here.
+ Adjust intrin call.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-comibf-1.c: Adjust asm check.
+ * gcc.target/i386/avx10_2-comibf-3.c: Ditto.
+ * gcc.target/i386/avx10_2-vcomsbf16-1.c: Move to...
+ * gcc.target/i386/avx10_2-vcomisbf16-1.c: ...here.
+ Adjust output and intrin call.
+ * gcc.target/i386/avx10_2-vcomsbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcomisbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/pr117495.c: Adjust asm check.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vfpclasspbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vfpclassbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vgetexppbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vgetexpbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-vgetexppbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vgetexpbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vfpclasspbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vfpclassbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx-1.c: Adjust builtin call.
+ * gcc.target/i386/sse-13.c: Ditto.
+ * gcc.target/i386/sse-23.c: Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-bf16-1.c: Adjust output and intrin
+ call.
+ * gcc.target/i386/avx10_2-512-vrsqrtpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vrsqrtbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vscalefpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vscalefbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vsqrtnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vsqrtbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-bf16-1.c: Adjust output and intrin
+ call.
+ * gcc.target/i386/avx10_2-vrsqrtpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vrsqrtbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vscalefpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vscalefbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vsqrtnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vsqrtbf16-2.c: ...here.
+ Adjust intrin call.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vgetmantpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vgetmantbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vreducenepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vreducebf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vrndscalenepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vrndscalebf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-bf16-1.c: Adjust output and intrin
+ call.
+ * gcc.target/i386/avx10_2-vgetmantpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vgetmantbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vreducenepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vreducebf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vrndscalenepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vrndscalebf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx-1.c: Adjust builtin call.
+ * gcc.target/i386/sse-13.c: Ditto.
+ * gcc.target/i386/sse-23.c: Ditto.
+ * gcc.target/i386/sse-14.c: Adjust intrin call.
+ * gcc.target/i386/sse-22.c: Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-minmax-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vminmaxnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vminmaxbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-minmax-1.c: Adjust output and intrin
+ call.
+ * gcc.target/i386/avx10_2-vminmaxnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vminmaxbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx-1.c: Adjust builtin call.
+ * gcc.target/i386/sse-13.c: Ditto.
+ * gcc.target/i386/sse-23.c: Ditto.
+ * gcc.target/i386/sse-14.c: Adjust intrin call.
+ * gcc.target/i386/sse-22.c: Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-bf-vector-cmpp-1.c: Move to...
+ * gcc.target/i386/avx10_2-512-bf16-vector-cmp-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-512-bf-vector-smaxmin-1.c: Move to...
+ * gcc.target/i386/avx10_2-512-bf16-vector-smaxmin-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-512-vcmppbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vcmpbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vmaxpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vmaxbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vminpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vminbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-bf-vector-cmpp-1.c: Move to...
+ * gcc.target/i386/avx10_2-bf16-vector-cmp-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-bf-vector-smaxmin-1.c: Move to...
+ * gcc.target/i386/avx10_2-bf16-vector-smaxmin-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-partial-bf-vector-smaxmin-1.c: Move to...
+ * gcc.target/i386/avx10_2-partial-bf16-vector-smaxmin-1.c: ...here.
+ * gcc.target/i386/avx10_2-vcmppbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vcmpbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vmaxpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vmaxbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vminpbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vminbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/part-vect-vec_cmpbf.c: Adjust asm check.
+ * gcc.target/i386/avx-1.c: Adjust builtin call.
+ * gcc.target/i386/sse-13.c: Ditto.
+ * gcc.target/i386/sse-23.c: Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-bf-vector-fma-1.c: Move to...
+ * gcc.target/i386/avx10_2-512-bf16-vector-fma-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-512-vfmaddXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vfmaddXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vfmsubXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vfmsubXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vfnmaddXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vfnmaddXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-512-vfnmsubXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vfnmsubXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-bf-vector-fma-1.c: Move to...
+ * gcc.target/i386/avx10_2-bf16-vector-fma-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-partial-bf-vector-fma-1.c: Move to...
+ * gcc.target/i386/avx10_2-partial-bf16-vector-fma-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-vfmaddXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vfmaddXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vfmsubXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vfmsubXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vfnmaddXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vfnmaddXXXbf16-2.c: ...here.
+ Adjust intrin call.
+ * gcc.target/i386/avx10_2-vfnmsubXXXnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vfnmsubXXXbf16-2.c: ...here.
+ Adjust intrin call.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ * gcc.target/i386/avx10_2-512-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-512-bf-vector-operations-1.c: Move to ...
+ * gcc.target/i386/avx10_2-512-bf16-vector-operations-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-512-vaddnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vaddbf16-2.c: ...here. Adjust
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vdivnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vdivbf16-2.c: ...here. Adjust
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vmulnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vmulbf16-2.c: ...here. Adjust
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vrcppbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vrcpbf16-2.c: ...here. Adjust
+ intrin call.
+ * gcc.target/i386/avx10_2-512-vsubnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-512-vsubbf16-2.c: ...here. Adjust
+ intrin call.
+ * gcc.target/i386/avx10_2-bf16-1.c: Adjust output and
+ intrin call.
+ * gcc.target/i386/avx10_2-bf-vector-operations-1.c: Move to ....
+ * gcc.target/i386/avx10_2-bf16-vector-operations-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-partial-bf-vector-fast-math-1.c: Move to...
+ * gcc.target/i386/avx10_2-partial-bf16-vector-fast-math-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-partial-bf-vector-operations-1.c: Move to...
+ * gcc.target/i386/avx10_2-partial-bf16-vector-operations-1.c: ...here.
+ Adjust asm check.
+ * gcc.target/i386/avx10_2-vaddnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vaddbf16-2.c: ...here. Adjust intrin call.
+ * gcc.target/i386/avx10_2-vdivnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vdivbf16-2.c: ...here. Adjust intrin call.
+ * gcc.target/i386/avx10_2-vmulnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vmulbf16-2.c: ...here. Adjust intrin call.
+ * gcc.target/i386/avx10_2-vrcppbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vrcpbf16-2.c: ...here. Adjust intrin call.
+ * gcc.target/i386/avx10_2-vsubnepbf16-2.c: Move to...
+ * gcc.target/i386/avx10_2-vsubbf16-2.c: ...here. Adjust intrin call.
+ * lib/target-supports.exp (check_effective_target_avx10_2):
+ Adjust asm usage.
+ (check_effective_target_avx10_2_512): Ditto.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ PR target/118270
+ PR target/118609
+ * gcc.target/i386/amxmovrs-t2rpntlvw-2.c: Move to...
+ * gcc.target/i386/amxmovrs-2rpntlvwrs-2.c: ...here.
+ * gcc.target/i386/amxtranspose-2rpntlvw-2.c: Add "t1" hint test.
+
+2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
+
+ * gcc.target/i386/vnniint16-auto-vectorize-4.c: Append
+ -march=x86-64-v3.
+ * gcc.target/i386/vnniint8-auto-vectorize-4.c: Ditto.
+
2025-01-22 Arsen Arsenović <arsen@aarsen.me>
* gcc.dg/driver-nostdlibstar.c: New test.
diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 81b9c8a1e763..d2358a323d92 100644
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,9 @@
+2025-01-23 Jan Hubicka <jh@suse.cz>
+
+ PR target/80813
+ * include/bits/stl_bvector.h (vector<bool, _Alloc>::operator []): Do
+ not use iterators.
+
2025-01-20 Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
PR libstdc++/118185
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