[PATCH v2] RISC-V: Use builtin for ffs and ffsll while supported extension available

[Adhemerval Zanella Netto]

On 08/11/24 10:41, Julian Zhu wrote:
> Hardware ctz instructions are available in the RISC-V Zbb and XTheadBb extension. With special `-march` flags defined, we can generate more simplified code compared to the generic implementation of `ffs`/`ffsll`.
> 
> Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>

LGTM, thanks.

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>

> ---
>  sysdeps/riscv/math-use-builtins-ffs.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>  create mode 100644 sysdeps/riscv/math-use-builtins-ffs.h
> 
> diff --git a/sysdeps/riscv/math-use-builtins-ffs.h b/sysdeps/riscv/math-use-builtins-ffs.h
> new file mode 100644
> index 0000000000..97d13e9496
> --- /dev/null
> +++ b/sysdeps/riscv/math-use-builtins-ffs.h
> @@ -0,0 +1,10 @@
> +#if __GNUC_PREREQ (12, 0) && defined __riscv_zbb
> +#  define USE_FFS_BUILTIN 1
> +#  define USE_FFSLL_BUILTIN 1
> +#elif __GNUC_PREREQ (13, 0) && defined __riscv_xtheadbb
> +#  define USE_FFS_BUILTIN 0
> +#  define USE_FFSLL_BUILTIN 1
> +#else
> +#  define USE_FFS_BUILTIN 0
> +#  define USE_FFSLL_BUILTIN 0
> +#endif