[PATCH v2 1/4] aarch64: Use 64-bit variable to access the special registers

[Sam James]

Adhemerval Zanella Netto <adhemerval.zanella@linaro.org> writes:

> On 10/01/25 18:04, H.J. Lu wrote:
>> On Sat, Jan 11, 2025 at 2:15 AM Adhemerval Zanella
>> <adhemerval.zanella@linaro.org> wrote:
>>>
>>> clang issues:
>>>
>>>   error: value size does not match register size specified by the
>>>   constraint and modifier [-Werror,-Wasm-operand-widths]
>>>
>>> while tryng to use 32 bit variables with 'mrs' to get/set the
>>> fpsr, dczid_el0, and ctr.
>>> ---
>>>  sysdeps/aarch64/fpu/fpu_control.h             | 36 +++++++++++++------
>>>  sysdeps/aarch64/fpu/fraiseexcpt.c             |  3 +-
>>>  sysdeps/aarch64/sfp-machine.h                 |  2 +-
>>>  .../unix/sysv/linux/aarch64/cpu-features.c    |  2 +-
>>>  sysdeps/unix/sysv/linux/aarch64/sysconf.c     |  2 +-
>>>  5 files changed, 30 insertions(+), 15 deletions(-)
>>>
>>> diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
>>> index 5df6da3ffc..a93dbf5efa 100644
>>> --- a/sysdeps/aarch64/fpu/fpu_control.h
>>> +++ b/sysdeps/aarch64/fpu/fpu_control.h
>>> @@ -29,17 +29,31 @@
>>>  # define _FPU_GETFPSR(fpsr) (fpsr = __builtin_aarch64_get_fpsr ())
>>>  # define _FPU_SETFPSR(fpsr) __builtin_aarch64_set_fpsr (fpsr)
>>>  #else
>>> -# define _FPU_GETCW(fpcr) \
>>> -  __asm__ __volatile__ ("mrs   %0, fpcr" : "=r" (fpcr))
>>> -
>>> -# define _FPU_SETCW(fpcr) \
>>> -  __asm__ __volatile__ ("msr   fpcr, %0" : : "r" (fpcr))
>>> -
>>> -# define _FPU_GETFPSR(fpsr) \
>>> -  __asm__ __volatile__ ("mrs   %0, fpsr" : "=r" (fpsr))
>>> -
>>> -# define _FPU_SETFPSR(fpsr) \
>>> -  __asm__ __volatile__ ("msr   fpsr, %0" : : "r" (fpsr))
>>> +# define _FPU_GETCW(fpcr)                                      \
>>> +  ({                                                           \
>>> +   __uint64_t __fpcr;                                          \
>>> +   __asm__ __volatile__ ("mrs  %0, fpcr" : "=r" (__fpcr));     \
>>> +   fpcr = __fpcr;                                              \
>>> +  })
>>> +
>>> +# define _FPU_SETCW(fpcr)                                      \
>>> +  ({                                                           \
>>> +   __uint64_t __fpcr = fpcr;                                   \
>>> +   __asm__ __volatile__ ("msr  fpcr, %0" : : "r" (__fpcr));    \
>>> +  })
>>> +
>>> +# define _FPU_GETFPSR(fpsr)                                    \
>>> +  ({                                                           \
>>> +   __uint64_t __fpsr;                                          \
>>> +   __asm__ __volatile__ ("mrs  %0, fpsr" : "=r" (__fpsr));     \
>>> +   fpsr = __fpsr;                                              \
>>> +  })
>>> +
>>> +# define _FPU_SETFPSR(fpsr)                                    \
>>> +  ({                                                           \
>>> +   __uint64_t __fpsr = fpsr;                                   \
>>> +   __asm__ __volatile__ ("msr  fpsr, %0" : : "r" (__fpsr));    \
>>> +  })
>>>  #endif
>>>
>>>  /* Reserved bits should be preserved when modifying register
>>> diff --git a/sysdeps/aarch64/fpu/fraiseexcpt.c b/sysdeps/aarch64/fpu/fraiseexcpt.c
>>> index bf5862a56e..518a6eb321 100644
>>> --- a/sysdeps/aarch64/fpu/fraiseexcpt.c
>>> +++ b/sysdeps/aarch64/fpu/fraiseexcpt.c
>>> @@ -19,11 +19,12 @@
>>>  #include <fenv.h>
>>>  #include <fpu_control.h>
>>>  #include <float.h>
>>> +#include <stdint.h>
>>>
>>>  int
>>>  __feraiseexcept (int excepts)
>>>  {
>>> -  int fpsr;
>>> +  uint64_t fpsr;
>>>    const float fp_zero = 0.0;
>>>    const float fp_one = 1.0;
>>>    const float fp_max = FLT_MAX;
>>> diff --git a/sysdeps/aarch64/sfp-machine.h b/sysdeps/aarch64/sfp-machine.h
>>> index a9ecdbf961..b41a9462df 100644
>>> --- a/sysdeps/aarch64/sfp-machine.h
>>> +++ b/sysdeps/aarch64/sfp-machine.h
>>> @@ -74,7 +74,7 @@ do {                                          \
>>>      const float fp_1e32 = 1.0e32f;                                     \
>>>      const float fp_zero = 0.0;                                         \
>>>      const float fp_one = 1.0;                                          \
>>> -    unsigned fpsr;                                                     \
>>> +    uint64_t fpsr;                                                     \
>>>      if (_fex & FP_EX_INVALID)                                          \
>>>        {                                                                        \
>>>          __asm__ __volatile__ ("fdiv\ts0, %s0, %s0"                     \
>>> diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
>>> index 26cf6d4a56..7ac228303f 100644
>>> --- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
>>> +++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
>>> @@ -128,7 +128,7 @@ init_cpu_features (struct cpu_features *cpu_features)
>>>    cpu_features->midr_el1 = midr;
>>>
>>>    /* Check if ZVA is enabled.  */
>>> -  unsigned dczid;
>>> +  uint64_t dczid;
>>>    asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
>>>
>>>    if ((dczid & DCZID_DZP_MASK) == 0)
>>> diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
>>> index c0df3af28c..bca2e0d286 100644
>>> --- a/sysdeps/unix/sysv/linux/aarch64/sysconf.c
>>> +++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c
>>> @@ -27,7 +27,7 @@ static long int linux_sysconf (int name);
>>>  long int
>>>  __sysconf (int name)
>>>  {
>>> -  unsigned ctr;
>>> +  unsigned long int ctr;
>> 
>> Should it be uint64_t?
>
> It makes sense, I will fix it.
>

The change is obviously OK, just for completeness.

>> 
>>>    /* Unfortunately, the registers that contain the actual cache info
>>>       (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux
>>> --
>>> 2.43.0
>>>
>> 
>>