ARM: enable interpreter, add locks code

[David Daney]

Daniel Jacobowitz wrote:
> On Wed, Jul 11, 2007 at 12:58:28PM -0700, David Daney wrote:
>> Andrew Haley wrote:
>>
>>> +/* Atomic compare and exchange.  These sequences are not actually
>>> +   atomic; there is a race if *ADDR != OLD_VAL and we are preempted
>>> +   between the two swaps.  However, they are very close to atomic, and
>>> +   are the best that a pre-ARMv6 implementation can do without
>>> +   operating system support.  LinuxThreads has been using these
>>> +   sequences for many years.  */
>> Wow!  That is terrible.
> 
> Actually it works very well :-)
> 

Until you get a random deadlock in a long running process.

It seems like the LinuxThreads bug for MIPS in glibc 2.2.5 that I spent 
about a week trying to figure out.  At least in that case upgrading to 
glibc 2.3.3 fixed things nicely.

David Daney