ARM: enable interpreter, add locks code

[David Daney]

Andrew Haley wrote:

> +/* Atomic compare and exchange.  These sequences are not actually
> +   atomic; there is a race if *ADDR != OLD_VAL and we are preempted
> +   between the two swaps.  However, they are very close to atomic, and
> +   are the best that a pre-ARMv6 implementation can do without
> +   operating system support.  LinuxThreads has been using these
> +   sequences for many years.  */

Wow!  That is terrible.

Is there some way to do proper synchronization if the target CPU 
supports it?

David Daney