a super regular RISC that encodes constants in immediate blocks.

[Michael Clark]

Hi Folks,

here is an idea expressed as a simple proof-of-concept simulator.

- https://github.com/michaeljclark/glyph/

I have been working on a proof-of-concept simulator for a RISC 
architecture with an immediate base register next to the program counter 
to split the front-end stream into independent instruction and constant 
streams. I named it glyph. it features a super-regular encoding scheme 
designed for vectorized decoding, and it uses a _i32x2_ vector of 
relative displacements in the link register to branch both instructions 
and constants at the same time. this evolved from thinking about a 
"virt" machine that was good for software to decode but could 
potentially be hardware.

I am still writing tests for it, but it is possible to test out the 
relative link register _(pc,ib)_ vector concept using subroutine branch 
displacements and constant block displacements in constant memory, which 
is read-only like instruction text. it has some interesting 
consequences. stack does not leak spilled absolute addresses so ASLR may 
be harder to bypass.

it uses flags for compare. register 0 can currently contain data. near 
branches are +/-512 bytes _(9-bit is the largest embedded immediate in 
the 16-bit format)_. the proof-of-concept has 8 registers, and there is 
a Python script for generating vectorized switch decoders for the 
variable-length instruction scheme. however, the proof-of-concept 
simulator currently only supports the 16-bit compressed opcode space.

it doesn't have a compiler or assembler yet. but considerable thought 
has gone into the design of the instruction format and the split 
instruction and constant streams. the 16-bit opcode space can access 
64-bit constants, but the 32-bit opcodes will support all typical 
constant sizes, and up to 64 read-write registers and more constants.

linker relocations are quite neat with this architecture. return from 
procedure needs a reloc due to the use of relative displacements in the 
link register. I am keen for feedback. there are a lot of details in the 
repo, including a Python script to explore combinatoric expansion for 
vectorized decoders.

it has a simpler length coding scheme than RISC-V at the expense of one 
bit of coding space in the 16-bit packet. as a result, it uses less 
wires and logic for length decoding of 64-bit instructions. it borrows 
an idea from LEB128. i.e. it is _super regular_. but we won't know how 
it will do on density until we have the 32-bit opcodes.

Michael