GCC used to store pointers in FP registers on aarch64

[Mark Rutland]

On Mon, Feb 24, 2025 at 10:46:42AM +0100, Attila Szegedi wrote:
> Hi folks,

Hi,

I've been pointed at this thread due to the reference to my Linux patch
series fixing some KVM FPSIMD/SVE/SME issues.

> I'm looking for a bit of a historic context for a fun GCC behavior we
> stumbled across. For... reasons we build some of our binaries using an
> older version of GCC (8.3.1, yes, we'll be upgrading soon, and no, this
> message is not about helping with an ancient version :-) )
> 
> We noticed that this version of GCC compiling on aarch64 will happily use
> FP registers to temporarily store/load pointers, so there'd be "fmov d9,
> x1" to store a pointer, and then later when it's used as a parameter to a
> function call we'll see "fmov x1, d9" etc. We noticed this while
> investigating some crashes that seemed to always occur in functions called
> with parameters loaded through this mechanism, on certain specific models
> of aarch64 CPUs.

Hmmm... IIUC d9 specifically should be preserved by callees per AAPCS64;
do you see this with specific registers? e.g. v8 to v15?

Are you able to share any more information about the configuration(s)
that you see this with, e.g.

* Which CPU(s)?

  If you're not able to say which CPU(s) specifically, knowing whether
  SVE and/or SME are present would be helpful.

* Which kernel version(s), assuming this is with Linux?

  If virtualization is involved, knowing the guest and host kernel
  versions would be helpful.

Thanks,
Mark.