How to target a processor with very primitive addressing modes?

[Mikael Pettersson]

I'm working on a GCC backend for an older processor with very
primitive addressing support. The only way to load from or store to
memory is to compute the address into a register, and then use that
register in the load or store instruction. There are no immediate or
register offsets in memory accesses.

So what I need is for GCC to transform any

y = *(r + x);

into

t = r + x;
y = *t;

and similarly for stores. The problem is that however I try to model
that (rewrites in define_expands, patterns in the define_insns, or
extra predicates and constraint letters) GCC goes into reload loops. I
suspect that reloading assumes it can use SP+offset addressing modes
without needing new temps.

My current workaround is to reserve a register as a hidden spill temp,
and invoke code from the insn patterns to change the output templates
to the equivalent of the above when needed, but it's not a good
solution.

Are there any targets in current GCC with similar constraints?

Do you have any other recommendations on how to deal with these
constraints in GCC?

Thanks in advance,

/Mikael

(p.s. please CC me on any replies as I'm not subscribed to this mailing list)