Register allocation cost question

[Andrew Stubbs]

On 11/10/2023 07:54, Chung-Lin Tang wrote:
> 
> 
> On 2023/10/10 11:11 PM, Andrew Stubbs wrote:
>> Hi all,
>>
>> I'm trying to add a new register set to the GCN port, but I've hit a
>> problem I don't understand.
>>
>> There are 256 new registers (each 2048 bit vector register) but the
>> register file has to be divided between all the running hardware
>> threads; if you can use fewer registers you can get more parallelism,
>> which means that it's important that they're allocated in order.
>>
>> The problem is that they're not allocated in order. Somehow the IRA pass
>> is calculating different costs for the registers within the class. It
>> seems to prefer registers a32, a96, a160, and a224.
>>
>> The internal regno are 448, 512, 576, 640. These are not random numbers!
>> They all have zero for the 6 LSB.
>>
>> What could cause this? Did I overrun some magic limit? What target hook
>> might I have miscoded?
>>
>> I'm also seeing wrong-code bugs when I allow more than 32 new registers,
>> but that might be an unrelated problem. Or the allocation is broken? I'm
>> still analyzing this.
>>
>> If it matters, ... the new registers can't be used for general purposes,
>> so I'm trying to set them up as a temporary spill destination. This
>> means they're typically not busy. It feels like it shouldn't be this
>> hard... :(
> 
> Have you tried experimenting with REG_ALLOC_ORDER? I see that the GCN port currently isn't using this target macro.

The default definition is 0,1,2,3,4.... and is already the desired 
behaviour.

Andrew