RFC: New mechanism for hard reg operands to inline asm

[Andreas Krebbel]

On 6/4/21 8:18 PM, Paul Koning wrote:
...
> Yes, I would think this should be made a general mechanism that any target could use.
> 
> I wonder if instead of creating a new mechanism you could do this simply by creating new constraint names, where each name matches exactly one hard register.  That's roughly what this amounts to, isn't it? 

I thought about this as well but I'm not sure this would work well without changing LRA. It would
mean to introduce many register classes with single registers. The presence of many "sparse"
register classes to my understanding would affect register allocation.

Perhaps it would work to just emit all the moves into or out of hard regs at expand time.

Andreas