New x86-64 micro-architecture levels

Mallappa, Premachandra
Tue Jul 21 16:05:36 GMT 2020

[AMD Public Use]

Hi Floarian,

> I'm including a proposal for the levels below.  I use single letters for them, but I expect that the concrete implementation of this proposal will use 
> names like “x86-100”, “x86-101”, like in the glibc patch referenced above.  (But we can discuss other approaches.)

Personally I am not a big fan of this, for 2 reasons 
1. uses just x86 in name on x86_64 as well
2. 100/101 not very intuitive

> * Level A
> * Level B
> This step is so small that it probably can be dropped, unless the benefits from using VEX encoding are truly significant.

Yes, Agree, the delta is too small, can be clubbed into A or C.

> * Level C
> * Level D

Others are inline with the what we expect as logical grouping.

As you mentioned it is not easy tackle this,
Also we would also like to have dynamic loader support for "zen" / "zen2" as a version of "Level D" and takes preference over Level D,
which may have super-optimized libraries from AMD or other vendors.
These libraries are expected to be optimized according to micro-architectural details, not just ISA.

Probably we can discuss this on the hwcaps thread.


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