New x86-64 micro-architecture levels
Mon Jul 13 07:55:29 GMT 2020
* Joseph Myers:
> On Fri, 10 Jul 2020, Florian Weimer via Gcc wrote:
>> * Level A
>> CMPXCHG16B, LAHF/SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSSE3
>> This is one step above the K8 baseline and corresponds to a mainline CPU
>> model ca. 2008 to 2011. It is also implemented by recent-ish
>> generations of Intel Atom server CPUs (although I haven't tested the
>> latest version). A 32-bit variant would have to list many additional
>> CPU features here.
> FWIW, this is also the limit of what can be run under QEMU emulation, as
> QEMU lacks support for AVX and newer instruction set features.
Oh, I had forgotten about. I should have Cc:ed the QEMU folks as well.
We'll need to make sure that we have matching CPU models in
QEMU/libvirt, even for the levels that do not have TCG support.
valgrind is another consumer, but in my tests, it was mostly okay with
AVX2 code (but that was without auto-vectorization). AVX-512 is a
different matter, but that is also much further out.
> On the other hand, virtual machines seem liable to report something closer
> to the K8 baseline to the guest OS, missing the level A features, even
> when the underlying hardware supports everything in level B or level C.
They do this to support migration. I'm suspect that in many cases,
those are just configuration errors. That's why I want at least one
major distribution to switch to Level C as the baseline, to clean the
pipes. Then even those distributions that depend on run-time selection
for performance-critical code will benefit. 8-/
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