Even numbered register pairs restriction on some instructions

[Paul Koning]

> On Sep 3, 2018, at 1:25 PM, Matthew Malcomson <matthew.malcomson@arm.com> wrote:
> 
>>> 
>>> Thanks for the suggestions,
>>> I've had a look into these, and unfortunately it seems they have the same problem I've been hitting before.
>>> 
>>> The use of the TARGET_HARD_REGNO_MODE_OK macro limits all uses of registers in a given mode (so that we wouldn't be able to use register pairs beginning with odd registers for other instructions), while using an EVEN_REGS register class won't work in modes that span more than one hard register (as all hard registers covered by a pseudo register must be in the same class).
>> Is that so?  I don't remember that restriction, and certainly pdp11 does not do this.  Could that be why LRA is failing in some of my tests?  The "old" reload pass makes no objections.
>> 
>> Note though that there are two possible ways to look at this.
>> 
>> 1. Is there a register class such that all of the hard registers for a given mode are in that class?
>> 
>> 2. Is the value returned by REGNO_REG_CLASS the same for each of the hard registers of a register pair?
>> 
>> For pdp11, (1) is true (they are both members of GENERAL_REGS) while (2) is false (for the even register, GENERAL_REGS is returned, vs. MUL_REGS for the odd one).
>> 
>> 	paul
>> 
> Apologies, I was unclear there.
> 
> When I said "all hard registers covered by a pseudo register must be in the same class" I meant "in order for a register constraint to that class to be satisfied".
> 
> i.e. if you were to use the "d" constraint in the SI operand of the "mulhisi3" pattern, then that constraint would not allow any register pair to be used since all register pairs use an odd register.
> 
> That is why "register classes cannot be used to enforce a requirement for a register pair to start with an even-numbered register" as mentioned in https://gcc.gnu.org/onlinedocs/gccint/Register-Classes.html <https://gcc.gnu.org/onlinedocs/gccint/Register-Classes.html> .
> 
> Matthew

I see what you mean.  You want, say, SImode to be sometimes in an even/odd pair, and sometimes in any pair.  I'd like the same thing, in fact, or more generally still, I'd like SImode sometimes just to be a pair of HImode values that don't have to be both in registers at all, never mind in adjacent registers.  There doesn't seem to be a way to do that.  So pdp11, for example, always has SImode in even/odd pairs even though only MUL and DIV require that, no one else.

	paul