Potential bug on Cortex-M due to used registers/interrupts.

[David Brown]

On 16/11/17 17:54, Vitalijus Jefišovas wrote:
> On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
> other registers onto the psp stack, and then jumps to interrupt routine,
> when it finishes, NVIC restores these registers, and jumps back to user’s
> function.
> What is happening under the hood, NVIC only stacks 4 registers, r0, r1, r2,
> r3. The other ones r4-r12 is developer’s responsibility.
> I was looking at assembly code generated by GCC and there are plenty of
> instructions using r4-r12 registers.
> 
> 
> 
> How does GCC handle scenario when execution is switched to unknown
> procedure, which changes all of these registers?
> 

These other registers - r4 to r12 - are "callee saved".  That means that
a C function that uses them will first save the old values (push them
onto the stack), and will restore them at function exit.  So the C
compiler can generate a normal function with normal ARM eabi linkage and
calling conventions, and use it directly for an interrupt function (this
is one of the nice features of the Cortex-M architecture).  "caller
saved" registers, r0-r3 - the ones that the C function can use freely -
are saved by the hardware.  The others are saved by compiler-generated
instructions as needed.