Potential bug on Cortex-M due to used registers/interrupts.

[Vitalijus Jefišovas]

On Cortex-M mcu’s, when interrupt happens, NVIC copies r0-r3 and couple
other registers onto the psp stack, and then jumps to interrupt routine,
when it finishes, NVIC restores these registers, and jumps back to user’s
function.
What is happening under the hood, NVIC only stacks 4 registers, r0, r1, r2,
r3. The other ones r4-r12 is developer’s responsibility.
I was looking at assembly code generated by GCC and there are plenty of
instructions using r4-r12 registers.



How does GCC handle scenario when execution is switched to unknown
procedure, which changes all of these registers?

Regards.