Implementing TI mode (128-bit) and the 2nd pipeline for the MIPS R5900

[Richard Henderson]

On 03/09/2016 08:45 AM, Woon yung Liu wrote:
> 3. due to the current register size (UNITS_PER_WORD) definition, allocating
> a  TI mode register will cause two consecutive registers to be allocated instead
> (like the HILO pseudo register) of one (other than just being wrong, it is
> probably wasteful).
>
> Due to number 3, that also means that I cannot actually properly implement
> support for any vector mode because they're all 128-bit vectors. :(

Why do you believe that not using TImode precludes you implementing any vector 
support?  I don't think you need to touch TImode at all.  Just implement 
V16QImode, V8HImode and maybe V4SImode.

These modes can be special cased within mips_hard_regno_nregs and 
mips_class_max_nregs to only consume one register.

> The LQ/SQ instructions, if not used with the other MMI instructions, could
> also be used to speed up memory copying. But they operate on the full
> 128-bit GPRs, and are hence unusable without a 128-bit mode.

But you'll have at least one 128-bit mode (and maybe 3).
The memcpy expander will simply have to be taught to use them.



r~