Instruction scheduling for the R5900's 2 integer pipelines

[Woon yung Liu]

>There was a time where GCC would generate mult/multiply-add instructions 

> that would issue into the 2nd R5900 pipeline.
>
>It's been 15+ years since I looked at that problem, but IIRC I twiddled 
>the old register allocator, along with the expected changes in the 
>pipeline and constraints for the mul/mul-add insns in the mips backend 
>to exploit the dual multiply pipes on the r5900.
>
>The key was to realize that because selection of the pipeline is static 
>based on the registers used, you have to look at this as a register 
>allocation problem.
>
>You might dig out the old Cygnus releases.  They may provide clues, 
>particularly on the register allocation tweak.
>
>Jeff


Right now, I do have an old homebrew GCC v3.2.2 port to study as well, but I didn't follow everything from it because I didn't want to risk including obsolete constructs.
Thanks for the information on the old Cygnus port. I'll try to scrape together a working system with it.