Help porting to lra

[shmeel gutl]

I am trying to enable lra for my vliw architecture and I am encountering 
a problem of  "max number of generated reload insns". The problem seems 
elementary but I don't see the correction.

Consider
      r1 =r2+r3
     s1=r1+r4
     call func(r3)
     r5=s2+r1

where s registers are pseudo registers which ira maps to callee saved 
registers
and r registers are pseudo registers which ira maps to caller saved 
registers.
The inheritance pass sees that r1 is still live across a call so it 
generates a spill using split_reg. Call_save_p is true so it spills to a 
pseudo register which ends up getting the same hard register assignment 
as r1. Therefore nothing is solved, the new register is also live across 
the call.

The call to the emit_spill_move looks like it is expecting a memory 
destination but it is in fact receiving a pseudo register. Did I miss 
some kind of hook that makes the spill go to the stack? Reload gets it 
right.

Thanks,
Shmeel