[i386] Scalar DImode instructions on XMM registers

Ilya Enkovich enkovich.gnu@gmail.com
Wed May 20 08:17:00 GMT 2015


On 19 May 11:22, Vladimir Makarov wrote:
> On 05/18/2015 08:13 AM, Ilya Enkovich wrote:
> >2015-05-06 17:18 GMT+03:00 Ilya Enkovich <enkovich.gnu@gmail.com>:
> >Hi Vladimir,
> >
> >Could you please comment on this?
> >
> >
> Ilya, I think that the idea is worth to try but results might be
> mixed.  It is hard to say until you actually try it (as example, Jan
> implemented -fpmath=both and it looks a pretty good idea at least
> for me but when I checked SPEC2000 the results were not so good even
> with IRA/LRA).
> 
> Long ago I did some experiments and found that spilling into SSE
> would benefitial for Intel CPUs but not for AMD ones.  As I remember
> I also found that storing several scalar values into one SSE reg and
> extracting it when you need to do some (fp) arithmetics would
> benefitial for AMD but not for Intel CPUs.   In literature more
> general approach is called bitwise register allocator.  Actually it
> would be a pretty big IRA/LRA project from which some targets might
> benefit.

I suspect such things are not trivially done in IRA/LRA and want to make it as an independent optimization because its application seems to be quite narrow.

> 
> 
> As for the wrong code, it is hard for me to say anything w/o RA
> dumps.  If you send me the dump (-fira-verbose=16), i might say more
> what is going on.
> 
> 

Here are some dumps from my reproducer.  The problematic register is r108.

Thanks,
Ilya
-------------- next part --------------

;; Function test (test, funcdef_no=0, decl_uid=1933, cgraph_uid=0, symbol_order=0)

scanning new insn with uid = 79.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 5 (    1)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
Reg 119: local to bb 2 def dominates all uses has unique first use
Reg 125 uninteresting
Reg 118: local to bb 2 def dominates all uses has unique first use
Reg 126 uninteresting
Reg 127 uninteresting
Found def insn 26 for 119 to be not moveable
;; 2 loops found
;;
;; Loop 0
;;  header 0, latch 1
;;  depth 0, outer -1
;;  nodes: 0 1 2 3 4
;;
;; Loop 1
;;  header 3, latch 3
;;  depth 1, outer 0
;;  nodes: 3
;; 2 succs { 3 4 }
;; 3 succs { 3 4 }
;; 4 succs { 1 }
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
init_insns for 117: (insn_list:REG_DEP_TRUE 22 (nil))


test

Dataflow summary:
;;  invalidated by call 	 0 [ax] 1 [dx] 2 [cx] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [] 38 [] 39 [] 40 [] 41 [] 42 [] 43 [] 44 [] 45 [] 46 [] 47 [] 48 [] 49 [] 50 [] 51 [] 52 [] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 []
;;  hardware regs used 	 7 [sp] 16 [argp] 20 [frame]
;;  regular block artificial uses 	 6 [bp] 7 [sp] 16 [argp] 20 [frame]
;;  eh block artificial uses 	 6 [bp] 7 [sp] 16 [argp] 20 [frame]
;;  entry block defs 	 0 [ax] 1 [dx] 2 [cx] 6 [bp] 7 [sp] 16 [argp] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 29 [mm0] 30 [mm1] 31 [mm2]
;;  exit block uses 	 6 [bp] 7 [sp] 20 [frame]
;;  regs ever live 	 3[bx] 7[sp] 17[flags]
;;  ref usage 	r0={2d} r1={2d} r2={2d} r3={1d,1u} r6={1d,4u} r7={1d,7u} r8={1d} r9={1d} r10={1d} r11={1d} r12={1d} r13={1d} r14={1d} r15={1d} r16={1d,4u,1e} r17={5d,2u} r18={1d} r19={1d} r20={1d,4u} r21={2d} r22={2d} r23={2d} r24={1d} r25={1d} r26={1d} r27={1d} r28={1d} r29={2d} r30={2d} r31={2d} r32={1d} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r50={1d} r51={1d} r52={1d} r53={1d} r54={1d} r55={1d} r56={1d} r57={1d} r58={1d} r59={1d} r60={1d} r61={1d} r62={1d} r63={1d} r64={1d} r65={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r78={1d} r79={1d} r80={1d} r107={1d,1u} r108={2d,4u} r117={2d,5u,2e} r118={1d,1u} r119={1d,1u} r123={2d,3u} r124={2d,3u} r125={1d,1u} r126={1d,1u} r127={1d,1u} r128={2d,2u} r129={2d,2u} 
;;    total ref usage 160{110d,47u,3e} in 25{24 regular + 1 call} insns.
(note 21 0 24 NOTE_INSN_DELETED)
(note 24 21 79 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 79 24 22 2 (parallel [
            (set (reg:SI 107)
                (unspec:SI [
                        (const_int 0 [0])
                    ] UNSPEC_SET_GOT))
            (clobber (reg:CC 17 flags))
        ]) 694 {set_got}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (expr_list:REG_EQUIV (unspec:SI [
                    (const_int 0 [0])
                ] UNSPEC_SET_GOT)
            (expr_list:REG_CFA_FLUSH_QUEUE (nil)
                (nil)))))
(insn 22 79 23 2 (set (reg/v/f:SI 117 [ arr ])
        (mem/f/c:SI (reg/f:SI 16 argp) [2 arr+0 S4 A32])) small.c:6 90 {*movsi_internal}
     (expr_list:REG_EQUIV (mem/f/c:SI (reg/f:SI 16 argp) [2 arr+0 S4 A32])
        (nil)))
(note 23 22 26 2 NOTE_INSN_FUNCTION_BEG)
(insn 26 23 72 2 (set (reg:DI 119 [ MEM[(long long int *)arr_5(D) + 8B] ])
        (mem:DI (plus:SI (reg/v/f:SI 117 [ arr ])
                (const_int 8 [0x8])) [1 MEM[(long long int *)arr_5(D) + 8B]+0 S8 A64])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 72 26 27 2 (set (reg:DI 125)
        (mem:DI (plus:SI (reg/v/f:SI 117 [ arr ])
                (const_int 16 [0x10])) [1 MEM[(long long int *)arr_5(D) + 16B]+0 S8 A64])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 27 72 73 2 (set (subreg:V2DI (reg:DI 118 [ D.1960 ]) 0)
        (and:V2DI (subreg:V2DI (reg:DI 119 [ MEM[(long long int *)arr_5(D) + 8B] ]) 0)
            (subreg:V2DI (reg:DI 125) 0))) small.c:9 3487 {*andv2di3}
     (expr_list:REG_DEAD (reg:DI 125)
        (expr_list:REG_DEAD (reg:DI 119 [ MEM[(long long int *)arr_5(D) + 8B] ])
            (expr_list:REG_EQUAL (and:DI (mem:DI (plus:SI (reg/v/f:SI 117 [ arr ])
                            (const_int 8 [0x8])) [1 MEM[(long long int *)arr_5(D) + 8B]+0 S8 A64])
                    (mem:DI (plus:SI (reg/v/f:SI 117 [ arr ])
                            (const_int 16 [0x10])) [1 MEM[(long long int *)arr_5(D) + 16B]+0 S8 A64]))
                (nil)))))
(insn 73 27 28 2 (set (reg:DI 126)
        (mem:DI (reg/v/f:SI 117 [ arr ]) [1 *arr_5(D)+0 S8 A64])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 28 73 68 2 (set (subreg:V2DI (reg/v:DI 108 [ tmp ]) 0)
        (ior:V2DI (subreg:V2DI (reg:DI 118 [ D.1960 ]) 0)
            (subreg:V2DI (reg:DI 126) 0))) small.c:9 3489 {*iorv2di3}
     (expr_list:REG_DEAD (reg:DI 126)
        (expr_list:REG_DEAD (reg:DI 118 [ D.1960 ])
            (nil))))
(insn 68 28 77 2 (set (reg:V2DI 124)
        (subreg:V2DI (reg/v:DI 108 [ tmp ]) 0)) small.c:9 1203 {*movv2di_internal}
     (nil))
(insn 77 68 70 2 (set (reg:SI 128)
        (vec_select:SI (subreg:V4SI (reg:V2DI 124) 0)
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:9 3667 {*vec_extractv4si_0}
     (nil))
(insn 70 77 78 2 (set (reg:V2DI 124)
        (lshiftrt:V2DI (reg:V2DI 124)
            (const_int 32 [0x20]))) small.c:9 3129 {lshrv2di3}
     (nil))
(insn 78 70 29 2 (set (reg:SI 129 [+4 ])
        (vec_select:SI (subreg:V4SI (reg:V2DI 124) 0)
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:9 3667 {*vec_extractv4si_0}
     (expr_list:REG_DEAD (reg:V2DI 124)
        (nil)))
(note 29 78 30 2 NOTE_INSN_DELETED)
(insn 30 29 31 2 (parallel [
            (set (reg:CCZ 17 flags)
                (compare:CCZ (ior:SI (reg:SI 129 [+4 ])
                        (reg:SI 128))
                    (const_int 0 [0])))
            (clobber (scratch:SI))
        ]) small.c:10 447 {*iorsi_3}
     (expr_list:REG_DEAD (reg:SI 129 [+4 ])
        (expr_list:REG_DEAD (reg:SI 128)
            (nil))))
(jump_insn 31 30 59 2 (set (pc)
        (if_then_else (eq (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (label_ref:SI 51)
            (pc))) small.c:10 619 {*jcc_1}
     (expr_list:REG_DEAD (reg:CCZ 17 flags)
        (int_list:REG_BR_PROB 900 (nil)))
 -> 51)
(code_label 59 31 58 3 5 "" [1 uses])
(note 58 59 38 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 38 58 39 3 (set (mem:DI (reg/f:SI 7 sp) [0  S8 A32])
        (reg/v:DI 108 [ tmp ])) small.c:12 89 {*movdi_internal}
     (nil))
(insn 39 38 40 3 (set (reg:SI 3 bx)
        (reg:SI 107)) small.c:12 90 {*movsi_internal}
     (nil))
(call_insn 40 39 41 3 (call (mem:QI (symbol_ref:SI ("counter") [flags 0x41]  <function_decl 0x7fac403d5288 counter>) [0 counter S1 A8])
        (const_int 8 [0x8])) small.c:12 666 {*call}
     (expr_list:REG_DEAD (reg:SI 3 bx)
        (expr_list:REG_CALL_DECL (symbol_ref:SI ("counter") [flags 0x41]  <function_decl 0x7fac403d5288 counter>)
            (nil)))
    (expr_list (use (reg:SI 3 bx))
        (expr_list:DI (use (mem:DI (reg/f:SI 7 sp) [0  S8 A32]))
            (nil))))
(insn 41 40 74 3 (parallel [
            (set (reg/v/f:SI 117 [ arr ])
                (plus:SI (reg/v/f:SI 117 [ arr ])
                    (const_int 8 [0x8])))
            (clobber (reg:CC 17 flags))
        ]) small.c:13 220 {*addsi_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
(insn 74 41 42 3 (set (reg:DI 127)
        (mem:DI (plus:SI (reg/v/f:SI 117 [ arr ])
                (const_int -8 [0xfffffffffffffff8])) [1 MEM[base: arr_14, offset: 4294967288B]+0 S8 A64])) small.c:13 89 {*movdi_internal}
     (nil))
(insn 42 74 64 3 (set (subreg:V2DI (reg/v:DI 108 [ tmp ]) 0)
        (and:V2DI (subreg:V2DI (reg/v:DI 108 [ tmp ]) 0)
            (subreg:V2DI (reg:DI 127) 0))) small.c:13 3487 {*andv2di3}
     (expr_list:REG_DEAD (reg:DI 127)
        (nil)))
(insn 64 42 75 3 (set (reg:V2DI 123)
        (subreg:V2DI (reg/v:DI 108 [ tmp ]) 0)) small.c:13 1203 {*movv2di_internal}
     (nil))
(insn 75 64 66 3 (set (reg:SI 128)
        (vec_select:SI (subreg:V4SI (reg:V2DI 123) 0)
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:13 3667 {*vec_extractv4si_0}
     (nil))
(insn 66 75 76 3 (set (reg:V2DI 123)
        (lshiftrt:V2DI (reg:V2DI 123)
            (const_int 32 [0x20]))) small.c:13 3129 {lshrv2di3}
     (nil))
(insn 76 66 44 3 (set (reg:SI 129 [+4 ])
        (vec_select:SI (subreg:V4SI (reg:V2DI 123) 0)
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:13 3667 {*vec_extractv4si_0}
     (expr_list:REG_DEAD (reg:V2DI 123)
        (nil)))
(note 44 76 45 3 NOTE_INSN_DELETED)
(insn 45 44 46 3 (parallel [
            (set (reg:CCZ 17 flags)
                (compare:CCZ (ior:SI (reg:SI 129 [+4 ])
                        (reg:SI 128))
                    (const_int 0 [0])))
            (clobber (scratch:SI))
        ]) small.c:10 447 {*iorsi_3}
     (expr_list:REG_DEAD (reg:SI 129 [+4 ])
        (expr_list:REG_DEAD (reg:SI 128)
            (nil))))
(jump_insn 46 45 51 3 (set (pc)
        (if_then_else (ne (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (label_ref:SI 59)
            (pc))) small.c:10 619 {*jcc_1}
     (expr_list:REG_DEAD (reg:CCZ 17 flags)
        (int_list:REG_BR_PROB 9100 (nil)))
 -> 59)
(code_label 51 46 52 4 1 "" [1 uses])
(note 52 51 0 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
-------------- next part --------------

;; Function test (test, funcdef_no=0, decl_uid=1933, cgraph_uid=0, symbol_order=0)

rescanning insn with uid = 30.
rescanning insn with uid = 45.
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 6 (  1.2)
deleting insn with uid = 89.
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 6 (  1.2)
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 5 (    1)
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 5 (    1)
changing reg in insn 79
changing reg in insn 39
changing reg in insn 41
changing reg in insn 22
changing reg in insn 74
changing reg in insn 73
changing reg in insn 72
changing reg in insn 41
changing reg in insn 26
changing reg in insn 27
changing reg in insn 27
changing reg in insn 26
changing reg in insn 66
changing reg in insn 64
changing reg in insn 66
changing reg in insn 70
changing reg in insn 68
changing reg in insn 70
changing reg in insn 72
changing reg in insn 73
changing reg in insn 74
changing reg in insn 77
changing reg in insn 75
changing reg in insn 45
changing reg in insn 30
changing reg in insn 78
changing reg in insn 76
deleting insn with uid = 83.
deleting insn with uid = 39.
deleting insn with uid = 87.


try_optimize_cfg iteration 1

starting the processing of deferred insns
ending the processing of deferred insns
verify found no changes in insn with uid = 40.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 5 (    1)
df_worklist_dataflow_doublequeue:n_basic_blocks 5 n_edges 6 count 6 (  1.2)


test

Dataflow summary:
;;  invalidated by call 	 0 [ax] 1 [dx] 2 [cx] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 17 [flags] 18 [fpsr] 19 [fpcr] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [] 38 [] 39 [] 40 [] 41 [] 42 [] 43 [] 44 [] 45 [] 46 [] 47 [] 48 [] 49 [] 50 [] 51 [] 52 [] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 []
;;  hardware regs used 	 7 [sp]
;;  regular block artificial uses 	 7 [sp]
;;  eh block artificial uses 	 7 [sp] 16 [argp]
;;  entry block defs 	 0 [ax] 1 [dx] 2 [cx] 7 [sp] 21 [xmm0] 22 [xmm1] 23 [xmm2] 29 [mm0] 30 [mm1] 31 [mm2]
;;  exit block uses 	 7 [sp]
;;  regs ever live 	 0[ax] 1[dx] 3[bx] 4[si] 7[sp] 17[flags] 21[xmm0] 22[xmm1] 23[xmm2] 24[xmm3] 25[xmm4]
;;  ref usage 	r0={7d,3u} r1={5d,3u} r2={2d} r3={1d,1u} r4={2d,5u,2e} r7={1d,11u} r8={1d} r9={1d} r10={1d} r11={1d} r12={1d} r13={1d} r14={1d} r15={1d} r16={1e} r17={5d,2u} r18={1d} r19={1d} r21={9d,9u} r22={4d,2u} r23={4d,2u} r24={3d,3u} r25={3d,2u} r26={1d} r27={1d} r28={1d} r29={2d} r30={2d} r31={2d} r32={1d} r33={1d} r34={1d} r35={1d} r36={1d} r37={1d} r38={1d} r39={1d} r40={1d} r41={1d} r42={1d} r43={1d} r44={1d} r45={1d} r46={1d} r47={1d} r48={1d} r49={1d} r50={1d} r51={1d} r52={1d} r53={1d} r54={1d} r55={1d} r56={1d} r57={1d} r58={1d} r59={1d} r60={1d} r61={1d} r62={1d} r63={1d} r64={1d} r65={1d} r66={1d} r67={1d} r68={1d} r69={1d} r70={1d} r71={1d} r72={1d} r73={1d} r74={1d} r75={1d} r76={1d} r77={1d} r78={1d} r79={1d} r80={1d} 
;;    total ref usage 160{114d,43u,3e} in 30{29 regular + 1 call} insns.
(note 21 0 24 NOTE_INSN_DELETED)
(note 24 21 79 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn/f 79 24 22 2 (parallel [
            (set (reg:SI 3 bx [107])
                (unspec:SI [
                        (const_int 0 [0])
                    ] UNSPEC_SET_GOT))
            (clobber (reg:CC 17 flags))
        ]) 694 {set_got}
     (expr_list:REG_EQUIV (unspec:SI [
                (const_int 0 [0])
            ] UNSPEC_SET_GOT)
        (expr_list:REG_CFA_FLUSH_QUEUE (nil)
            (nil))))
(insn 22 79 23 2 (set (reg/v/f:SI 4 si [orig:117 arr ] [117])
        (mem/f/c:SI (plus:SI (reg/f:SI 7 sp)
                (const_int 48 [0x30])) [2 arr+0 S4 A32])) small.c:6 90 {*movsi_internal}
     (expr_list:REG_EQUIV (mem/f/c:SI (reg/f:SI 16 argp) [2 arr+0 S4 A32])
        (nil)))
(note 23 22 26 2 NOTE_INSN_FUNCTION_BEG)
(insn 26 23 72 2 (set (reg:DI 22 xmm1 [orig:119 MEM[(long long int *)arr_5(D) + 8B] ] [119])
        (mem:DI (plus:SI (reg/v/f:SI 4 si [orig:117 arr ] [117])
                (const_int 8 [0x8])) [1 MEM[(long long int *)arr_5(D) + 8B]+0 S8 A64])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 72 26 27 2 (set (reg:DI 21 xmm0 [125])
        (mem:DI (plus:SI (reg/v/f:SI 4 si [orig:117 arr ] [117])
                (const_int 16 [0x10])) [1 MEM[(long long int *)arr_5(D) + 16B]+0 S8 A64])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 27 72 73 2 (set (reg:V2DI 21 xmm0 [orig:118 D.1960 ] [118])
        (and:V2DI (reg:V2DI 21 xmm0 [125])
            (reg:V2DI 22 xmm1 [orig:119 MEM[(long long int *)arr_5(D) + 8B] ] [119]))) small.c:9 3487 {*andv2di3}
     (expr_list:REG_EQUAL (and:DI (mem:DI (plus:SI (reg/v/f:SI 4 si [orig:117 arr ] [117])
                    (const_int 8 [0x8])) [1 MEM[(long long int *)arr_5(D) + 8B]+0 S8 A64])
            (mem:DI (plus:SI (reg/v/f:SI 4 si [orig:117 arr ] [117])
                    (const_int 16 [0x10])) [1 MEM[(long long int *)arr_5(D) + 16B]+0 S8 A64]))
        (nil)))
(insn 73 27 81 2 (set (reg:DI 22 xmm1 [126])
        (mem:DI (reg/v/f:SI 4 si [orig:117 arr ] [117]) [1 *arr_5(D)+0 S8 A64])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 81 73 28 2 (set (reg:V2DI 25 xmm4 [132])
        (reg:V2DI 21 xmm0 [orig:118 D.1960 ] [118])) small.c:9 1203 {*movv2di_internal}
     (nil))
(insn 28 81 82 2 (set (reg:V2DI 25 xmm4 [132])
        (ior:V2DI (reg:V2DI 25 xmm4 [132])
            (reg:V2DI 22 xmm1 [126]))) small.c:9 3489 {*iorv2di3}
     (nil))
(insn 82 28 88 2 (set (reg:V2DI 24 xmm3 [orig:108 tmp ] [108])
        (reg:V2DI 25 xmm4 [132])) small.c:9 1203 {*movv2di_internal}
     (nil))
(insn 88 82 68 2 (set (mem/c:DI (plus:SI (reg/f:SI 7 sp)
                (const_int 16 [0x10])) [3 %sfp+-16 S8 A128])
        (reg/v:DI 24 xmm3 [orig:108 tmp ] [108])) small.c:9 89 {*movdi_internal}
     (nil))
(insn 68 88 77 2 (set (reg:V2DI 21 xmm0 [124])
        (reg:V2DI 24 xmm3 [orig:108 tmp ] [108])) small.c:9 1203 {*movv2di_internal}
     (nil))
(insn 77 68 70 2 (set (reg:SI 1 dx [128])
        (vec_select:SI (reg:V4SI 21 xmm0 [124])
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:9 3667 {*vec_extractv4si_0}
     (nil))
(insn 70 77 78 2 (set (reg:V2DI 21 xmm0 [124])
        (lshiftrt:V2DI (reg:V2DI 21 xmm0 [124])
            (const_int 32 [0x20]))) small.c:9 3129 {lshrv2di3}
     (nil))
(insn 78 70 29 2 (set (reg:SI 0 ax [orig:129+4 ] [129])
        (vec_select:SI (reg:V4SI 21 xmm0 [124])
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:9 3667 {*vec_extractv4si_0}
     (nil))
(note 29 78 30 2 NOTE_INSN_DELETED)
(insn 30 29 31 2 (parallel [
            (set (reg:CCZ 17 flags)
                (compare:CCZ (ior:SI (reg:SI 0 ax [130])
                        (reg:SI 1 dx [128]))
                    (const_int 0 [0])))
            (clobber (reg:SI 0 ax [130]))
        ]) small.c:10 447 {*iorsi_3}
     (nil))
(jump_insn 31 30 59 2 (set (pc)
        (if_then_else (eq (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (label_ref:SI 51)
            (pc))) small.c:10 619 {*jcc_1}
     (int_list:REG_BR_PROB 900 (nil))
 -> 51)
(code_label 59 31 58 3 5 "" [1 uses])
(note 58 59 84 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 84 58 38 3 (set (reg/v:DI 0 ax [orig:108 tmp ] [108])
        (mem/c:DI (plus:SI (reg/f:SI 7 sp)
                (const_int 16 [0x10])) [3 %sfp+-16 S8 A128])) small.c:12 89 {*movdi_internal}
     (nil))
(insn 38 84 40 3 (set (mem:DI (reg/f:SI 7 sp) [0  S8 A32])
        (reg/v:DI 0 ax [orig:108 tmp ] [108])) small.c:12 89 {*movdi_internal}
     (nil))
(call_insn 40 38 41 3 (call (mem:QI (symbol_ref:SI ("counter") [flags 0x41]  <function_decl 0x7fac403d5288 counter>) [0 counter S1 A8])
        (const_int 8 [0x8])) small.c:12 666 {*call}
     (expr_list:REG_CALL_DECL (symbol_ref:SI ("counter") [flags 0x41]  <function_decl 0x7fac403d5288 counter>)
        (nil))
    (expr_list (use (reg:SI 3 bx))
        (expr_list:DI (use (mem:DI (reg/f:SI 7 sp) [0  S8 A32]))
            (nil))))
(insn 41 40 74 3 (parallel [
            (set (reg/v/f:SI 4 si [orig:117 arr ] [117])
                (plus:SI (reg/v/f:SI 4 si [orig:117 arr ] [117])
                    (const_int 8 [0x8])))
            (clobber (reg:CC 17 flags))
        ]) small.c:13 220 {*addsi_1}
     (nil))
(insn 74 41 85 3 (set (reg:DI 21 xmm0 [127])
        (mem:DI (plus:SI (reg/v/f:SI 4 si [orig:117 arr ] [117])
                (const_int -8 [0xfffffffffffffff8])) [1 MEM[base: arr_14, offset: 4294967288B]+0 S8 A64])) small.c:13 89 {*movdi_internal}
     (nil))
(insn 85 74 42 3 (set (reg:V2DI 23 xmm2 [135])
        (reg:V2DI 21 xmm0 [127])) small.c:13 1203 {*movv2di_internal}
     (nil))
(insn 42 85 86 3 (set (reg:V2DI 23 xmm2 [135])
        (and:V2DI (reg:V2DI 23 xmm2 [135])
            (mem/c:V2DI (plus:SI (reg/f:SI 7 sp)
                    (const_int 16 [0x10])) [3 %sfp+-16 S16 A128]))) small.c:13 3487 {*andv2di3}
     (nil))
(insn 86 42 89 3 (set (reg:V2DI 24 xmm3 [orig:108 tmp ] [108])
        (reg:V2DI 23 xmm2 [135])) small.c:13 1203 {*movv2di_internal}
     (nil))
(note 89 86 64 3 NOTE_INSN_DELETED)
(insn 64 89 75 3 (set (reg:V2DI 21 xmm0 [123])
        (reg:V2DI 24 xmm3 [orig:108 tmp ] [108])) small.c:13 1203 {*movv2di_internal}
     (nil))
(insn 75 64 66 3 (set (reg:SI 1 dx [128])
        (vec_select:SI (reg:V4SI 21 xmm0 [123])
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:13 3667 {*vec_extractv4si_0}
     (nil))
(insn 66 75 76 3 (set (reg:V2DI 21 xmm0 [123])
        (lshiftrt:V2DI (reg:V2DI 21 xmm0 [123])
            (const_int 32 [0x20]))) small.c:13 3129 {lshrv2di3}
     (nil))
(insn 76 66 44 3 (set (reg:SI 0 ax [orig:129+4 ] [129])
        (vec_select:SI (reg:V4SI 21 xmm0 [123])
            (parallel [
                    (const_int 0 [0])
                ]))) small.c:13 3667 {*vec_extractv4si_0}
     (nil))
(note 44 76 45 3 NOTE_INSN_DELETED)
(insn 45 44 46 3 (parallel [
            (set (reg:CCZ 17 flags)
                (compare:CCZ (ior:SI (reg:SI 0 ax [131])
                        (reg:SI 1 dx [128]))
                    (const_int 0 [0])))
            (clobber (reg:SI 0 ax [131]))
        ]) small.c:10 447 {*iorsi_3}
     (nil))
(jump_insn 46 45 51 3 (set (pc)
        (if_then_else (ne (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (label_ref:SI 59)
            (pc))) small.c:10 619 {*jcc_1}
     (int_list:REG_BR_PROB 9100 (nil))
 -> 59)
(code_label 51 46 52 4 1 "" [1 uses])
(note 52 51 80 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(note 80 52 0 NOTE_INSN_DELETED)
-------------- next part --------------
Starting decreasing number of live ranges...
Building IRA IR

Pass 0 for finding pseudo/allocno costs

    a14 (r129,l1) best GENERAL_REGS, allocno GENERAL_REGS
    a1 (r129,l0) best GENERAL_REGS, allocno GENERAL_REGS
    a13 (r128,l1) best GENERAL_REGS, allocno GENERAL_REGS
    a0 (r128,l0) best GENERAL_REGS, allocno GENERAL_REGS
    a16 (r127,l1) best NO_REGS, allocno NO_REGS
    a4 (r126,l0) best NO_REGS, allocno NO_REGS
    a7 (r125,l0) best NO_REGS, allocno NO_REGS
    a2 (r124,l0) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    a15 (r123,l1) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    a8 (r119,l0) best NO_REGS, allocno NO_REGS
    a5 (r118,l0) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    a12 (r117,l1) best GENERAL_REGS, allocno GENERAL_REGS
    a6 (r117,l0) best GENERAL_REGS, allocno GENERAL_REGS
    a11 (r108,l1) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    a3 (r108,l0) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    a10 (r107,l1) best GENERAL_REGS, allocno GENERAL_REGS
    a9 (r107,l0) best GENERAL_REGS, allocno GENERAL_REGS

  a0(r128,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:720,720 NO_REX_SSE_REGS:720,720 MMX_REGS:1890,1890 INT_SSE_REGS:1530,1530 ALL_REGS:27720,27720 MEM:360,360
  a1(r129,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:720,720 NO_REX_SSE_REGS:720,720 MMX_REGS:1890,1890 INT_SSE_REGS:1530,1530 ALL_REGS:27720,27720 MEM:360,360
  a2(r124,l0) costs: SSE_FIRST_REG:0,0 NO_REX_SSE_REGS:0,0 MEM:2790,2790
  a3(r108,l0) costs: SSE_FIRST_REG:0,15470 NO_REX_SSE_REGS:0,15470 MEM:1350,28650
  a4(r126,l0) costs: SSE_FIRST_REG:1440,1440 NO_REX_SSE_REGS:1440,1440 MEM:1350,1350
  a5(r118,l0) costs: SSE_FIRST_REG:0,0 NO_REX_SSE_REGS:0,0 MEM:1350,1350
  a6(r117,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:2880,24720 NO_REX_SSE_REGS:2880,24720 MMX_REGS:4590,40080 INT_SSE_REGS:3240,27810 ALL_REGS:65520,633360 MEM:720,9820
  a7(r125,l0) costs: SSE_FIRST_REG:1440,1440 NO_REX_SSE_REGS:1440,1440 MEM:1350,1350
  a8(r119,l0) costs: SSE_FIRST_REG:1440,1440 NO_REX_SSE_REGS:1440,1440 MEM:1350,1350
  a9(r107,l0) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:720,8000 NO_REX_SSE_REGS:720,8000 MMX_REGS:1170,13000 INT_SSE_REGS:810,9000 ALL_REGS:18720,208000 MEM:360,3090
  a10(r107,l1) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:7280,7280 NO_REX_SSE_REGS:7280,7280 MMX_REGS:11830,11830 INT_SSE_REGS:8190,8190 ALL_REGS:189280,189280 MEM:2730,2730
  a11(r108,l1) costs: SSE_FIRST_REG:15470,15470 NO_REX_SSE_REGS:15470,15470 MEM:27300,27300
  a12(r117,l1) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:21840,21840 NO_REX_SSE_REGS:21840,21840 MMX_REGS:35490,35490 INT_SSE_REGS:24570,24570 ALL_REGS:567840,567840 MEM:9100,9100
  a13(r128,l1) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:7280,7280 NO_REX_SSE_REGS:7280,7280 MMX_REGS:19110,19110 INT_SSE_REGS:15470,15470 ALL_REGS:280280,280280 MEM:3640,3640
  a14(r129,l1) costs: AREG:0,0 DREG:0,0 CREG:0,0 BREG:0,0 SIREG:0,0 DIREG:0,0 AD_REGS:0,0 Q_REGS:0,0 NON_Q_REGS:0,0 GENERAL_REGS:0,0 SSE_FIRST_REG:7280,7280 NO_REX_SSE_REGS:7280,7280 MMX_REGS:19110,19110 INT_SSE_REGS:15470,15470 ALL_REGS:280280,280280 MEM:3640,3640
  a15(r123,l1) costs: SSE_FIRST_REG:0,0 NO_REX_SSE_REGS:0,0 MEM:28210,28210
  a16(r127,l1) costs: SSE_FIRST_REG:14560,14560 NO_REX_SSE_REGS:14560,14560 MEM:13650,13650


Pass 1 for finding pseudo/allocno costs

    r129: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS
    r128: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS
    r127: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    a16 (r127,l1) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    r126: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    a4 (r126,l0) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    r125: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    a7 (r125,l0) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    r124: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    r123: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    r119: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    a8 (r119,l0) best NO_REX_SSE_REGS, allocno NO_REX_SSE_REGS
    r118: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    r117: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS
    r108: preferred NO_REX_SSE_REGS, alternative NO_REGS, allocno NO_REX_SSE_REGS
    r107: preferred GENERAL_REGS, alternative NO_REGS, allocno GENERAL_REGS

  a0(r128,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:1440,1440 NO_REX_SSE_REGS:1440,1440 MMX_REGS:2250,2250 INT_SSE_REGS:1620,1620 ALL_REGS:28080,28080 MEM:630,630
  a1(r129,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:1440,1440 NO_REX_SSE_REGS:1440,1440 MMX_REGS:2250,2250 INT_SSE_REGS:1620,1620 ALL_REGS:28080,28080 MEM:630,630
  a2(r124,l0) costs: NO_REX_SSE_REGS:0,0 MEM:3420,3420
  a3(r108,l0) costs: NO_REX_SSE_REGS:720,46220 MEM:2070,60310
  a4(r126,l0) costs: NO_REX_SSE_REGS:2160,2160 MEM:2160,2160
  a5(r118,l0) costs: NO_REX_SSE_REGS:2880,2880 MEM:4320,4320
  a6(r117,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:2880,24720 NO_REX_SSE_REGS:2880,24720 MMX_REGS:4680,40170 INT_SSE_REGS:3240,27810 ALL_REGS:65880,633720 MEM:720,9820
  a7(r125,l0) costs: NO_REX_SSE_REGS:3600,3600 MEM:3600,3600
  a8(r119,l0) costs: NO_REX_SSE_REGS:3600,3600 MEM:3600,3600
  a9(r107,l0) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:720,8000 NO_REX_SSE_REGS:720,8000 MMX_REGS:1170,13000 INT_SSE_REGS:810,9000 ALL_REGS:18720,208000 MEM:360,3090
  a10(r107,l1) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:7280,7280 NO_REX_SSE_REGS:7280,7280 MMX_REGS:11830,11830 INT_SSE_REGS:8190,8190 ALL_REGS:189280,189280 MEM:2730,2730
  a11(r108,l1) costs: NO_REX_SSE_REGS:45500,45500 MEM:58240,58240
  a12(r117,l1) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:21840,21840 NO_REX_SSE_REGS:21840,21840 MMX_REGS:35490,35490 INT_SSE_REGS:24570,24570 ALL_REGS:567840,567840 MEM:9100,9100
  a13(r128,l1) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:14560,14560 NO_REX_SSE_REGS:14560,14560 MMX_REGS:22750,22750 INT_SSE_REGS:16380,16380 ALL_REGS:283920,283920 MEM:6370,6370
  a14(r129,l1) costs: GENERAL_REGS:0,0 SSE_FIRST_REG:14560,14560 NO_REX_SSE_REGS:14560,14560 MMX_REGS:22750,22750 INT_SSE_REGS:16380,16380 ALL_REGS:283920,283920 MEM:6370,6370
  a15(r123,l1) costs: NO_REX_SSE_REGS:0,0 MEM:34580,34580
  a16(r127,l1) costs: NO_REX_SSE_REGS:21840,21840 MEM:21840,21840

   Insn 31(l0): point = 1
   Insn 30(l0): point = 3
   Insn 78(l0): point = 5
   Insn 70(l0): point = 7
   Insn 77(l0): point = 9
   Insn 68(l0): point = 11
   Insn 28(l0): point = 13
   Insn 73(l0): point = 15
   Insn 27(l0): point = 17
   Insn 72(l0): point = 19
   Insn 26(l0): point = 21
   Insn 22(l0): point = 23
   Insn 79(l0): point = 25
   Insn 46(l1): point = 28
   Insn 45(l1): point = 30
   Insn 76(l1): point = 32
   Insn 66(l1): point = 34
   Insn 75(l1): point = 36
   Insn 64(l1): point = 38
   Insn 42(l1): point = 40
   Insn 74(l1): point = 42
   Insn 41(l1): point = 44
   Insn 40(l1): point = 46
   Insn 39(l1): point = 48
   Insn 38(l1): point = 50
 a0(r128): [4..9]
 a1(r129): [4..5]
 a2(r124): [6..11]
 a3(r108): [1..13]
 a4(r126): [14..15]
 a5(r118): [14..17]
 a6(r117): [1..23]
 a7(r125): [18..19]
 a8(r119): [18..21]
 a9(r107): [1..25]
 a10(r107): [28..52]
 a11(r108): [28..52]
 a12(r117): [28..52]
 a13(r128): [31..36]
 a14(r129): [31..32]
 a15(r123): [33..38]
 a16(r127): [41..42]
      Moving ranges of a14r129 to a1r129:  [31..32]
      Moving ranges of a13r128 to a0r128:  [31..36]
 Rebuilding regno allocno list for 127
 Rebuilding regno allocno list for 123
      Moving ranges of a12r117 to a6r117:  [28..52]
      Moving ranges of a11r108 to a3r108:  [28..52]
      Moving ranges of a10r107 to a9r107:  [28..52]
Compressing live ranges: from 53 to 14 - 26%
Ranges after the compression:
 a0(r128): [8..11] [0..3]
 a1(r129): [8..9] [0..1]
 a2(r124): [2..3]
 a3(r108): [8..13] [0..3]
 a4(r126): [4..5]
 a5(r118): [4..5]
 a6(r117): [0..13]
 a7(r125): [6..7]
 a8(r119): [6..7]
 a9(r107): [0..13]
 a15(r123): [10..11]
 a16(r127): [12..13]
+++Allocating 96 bytes for conflict table (uncompressed size 136)
;; a0(r128,l0) conflicts: a1(r129,l0) a6(r117,l0) a9(r107,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a1(r129,l0) conflicts: a0(r128,l0) a6(r117,l0) a9(r107,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a2(r124,l0) conflicts: a3(r108,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a3(r108,l0) conflicts: a2(r124,l0) a15(r123,l0) a16(r127,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a4(r126,l0) conflicts: a5(r118,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a5(r118,l0) conflicts: a4(r126,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a6(r117,l0) conflicts: a1(r129,l0) a0(r128,l0) a9(r107,l0)
;;     total conflict hard regs: 3
;;     conflict hard regs: 3

;; a7(r125,l0) conflicts: a8(r119,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a8(r119,l0) conflicts: a7(r125,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a9(r107,l0) conflicts: a1(r129,l0) a0(r128,l0) a6(r117,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a15(r123,l0) conflicts: a3(r108,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

;; a16(r127,l0) conflicts: a3(r108,l0)
;;     total conflict hard regs:
;;     conflict hard regs:

  cp0:a1(r129)<->a15(r123)@113:shuffle
  cp1:a5(r118)<->a7(r125)@90:constraint
  cp2:a5(r118)<->a8(r119)@90:constraint
  cp3:a3(r108)<->a4(r126)@90:constraint
  cp4:a3(r108)<->a5(r118)@90:constraint
  cp5:a1(r129)<->a2(r124)@11:shuffle
  pref1:a9(r107)<-hr3@910
  regions=2, blocks=5, points=14
    allocnos=17 (big 0), copies=6, conflicts=0, ranges=15

**** Allocnos coloring:


  Loop 0 (parent -1, header bb2, depth 0)
    bbs: 4 3 2
    all: 0r128 1r129 2r124 3r108 4r126 5r118 6r117 7r125 8r119 9r107 15r123 16r127
    modified regnos: 107 108 117 118 119 123 124 125 126 127 128 129
    border:
    Pressure: GENERAL_REGS=4 NO_REX_SSE_REGS=2
    Hard reg set forest:
      0:( 0-6 8-15 21-36)@0
        1:( 0-6)@28000
          2:( 0-2 4-6)@19640
        3:( 21-28)@78880
      Spill a3(r108,l0)
      Allocno a0r128 of GENERAL_REGS(7) has 7 avail. regs  0-6, node:  0-6 (confl regs =  7-79)
      Allocno a1r129 of GENERAL_REGS(7) has 7 avail. regs  0-6, node:  0-6 (confl regs =  7-79)
      Allocno a2r124 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Allocno a4r126 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Allocno a5r118 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Allocno a6r117 of GENERAL_REGS(7) has 6 avail. regs  0-2 4-6, node:  0-2 4-6 (confl regs =  3 7-79)
      Allocno a7r125 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Allocno a8r119 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Allocno a9r107 of GENERAL_REGS(7) has 4 avail. regs  3-6, ^node:  0-6 (confl regs =  7-79)
      Allocno a15r123 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Allocno a16r127 of NO_REX_SSE_REGS(8) has 8 avail. regs  21-28, node:  21-28 (confl regs =  0-20 29-79)
      Forming thread by copy 0:a1r129-a15r123 (freq=113):
        Result (freq=6550): a1r129(2000) a15r123(4550)
      Forming thread by copy 1:a5r118-a7r125 (freq=90):
        Result (freq=360): a5r118(180) a7r125(180)
      Forming thread by copy 5:a1r129-a2r124 (freq=11):
        Result (freq=7000): a1r129(2000) a2r124(450) a15r123(4550)
      Pushing a8(r119,l0)(cost 0)
      Pushing a4(r126,l0)(cost 0)
      Pushing a7(r125,l0)(cost 0)
      Pushing a5(r118,l0)(cost 0)
      Pushing a9(r107,l0)(cost 0)
      Pushing a16(r127,l0)(cost 0)
      Pushing a0(r128,l0)(cost 0)
      Pushing a6(r117,l0)(cost 0)
      Pushing a2(r124,l0)(cost 0)
      Pushing a1(r129,l0)(cost 0)
      Pushing a15(r123,l0)(cost 0)
      Popping a15(r123,l0)  -- assign reg 21
      Popping a1(r129,l0)  -- assign reg 0
      Popping a2(r124,l0)  -- assign reg 21
      Popping a6(r117,l0)  -- assign reg 4
      Popping a0(r128,l0)  -- assign reg 1
      Popping a16(r127,l0)  -- assign reg 21
      Popping a9(r107,l0)  -- assign reg 3
      Popping a5(r118,l0)  -- assign reg 21
      Popping a7(r125,l0)  -- assign reg 21
      Popping a4(r126,l0)  -- assign reg 22
      Popping a8(r119,l0)  -- assign reg 22
Disposition:
    9:r107 l0     3    3:r108 l0   mem    6:r117 l0     4    5:r118 l0    21
    8:r119 l0    22   15:r123 l0    21    2:r124 l0    21    7:r125 l0    21
    4:r126 l0    22   16:r127 l0    21    0:r128 l0     1    1:r129 l0     0
New iteration of spill/restore move
+++Costs: overall 92570, reg 32260, mem 60310, ld 0, st 0, move 0
+++       move loops 0, new jumps 0
      Creating newreg=130
Removing SCRATCH in insn #30 (nop 0)
      Creating newreg=131
Removing SCRATCH in insn #45 (nop 0)

********** Local #1: **********

	   Spilling non-eliminable hard regs: 7
New elimination table:
Can eliminate 16 to 7 (offset=32, prev_offset=0)
Can eliminate 16 to 6 (offset=4, prev_offset=0)
Can eliminate 20 to 7 (offset=16, prev_offset=0)
Can eliminate 20 to 6 (offset=-12, prev_offset=0)
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 79:  (0) =r {set_got}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 22:  (0) =r  (1) g {*movsi_internal}
            0 Non input pseudo reload: reject++
          alt=0,overall=13,losers=2,rld_nregs=2
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=1,overall=19,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=6,overall=14,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=7,overall=14,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=8,overall=20,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            alt=9,overall=16,losers=1 -- refuse
            0 Costly set: reject++
            alt=12: Bad operand -- refuse
            0 Costly set: reject++
            1 Costly loser: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
          alt=13,overall=611,losers=1,rld_nregs=1
            0 Costly set: reject++
          alt=14,overall=1,losers=0,rld_nregs=0
	 Choosing alt 14 in insn 26:  (0) *v  (1) m {*movdi_internal}
            0 Non input pseudo reload: reject++
          alt=0,overall=13,losers=2,rld_nregs=2
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=1,overall=19,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=6,overall=14,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=7,overall=14,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=8,overall=20,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            alt=9,overall=16,losers=1 -- refuse
            0 Costly set: reject++
            alt=12: Bad operand -- refuse
            0 Costly set: reject++
            1 Costly loser: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
          alt=13,overall=611,losers=1,rld_nregs=1
            0 Costly set: reject++
          alt=14,overall=1,losers=0,rld_nregs=0
	 Choosing alt 14 in insn 72:  (0) *v  (1) m {*movdi_internal}
          alt=0,overall=6,losers=1,rld_nregs=1
          alt=0,overall=0,losers=0,rld_nregs=0
  Commutative operand exchange in insn 27
	 Choosing alt 0 in insn 27:  (0) =x  (1) %0  (2) xm {*andv2di3}
            0 Non input pseudo reload: reject++
          alt=0,overall=13,losers=2,rld_nregs=2
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=1,overall=19,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=6,overall=14,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=7,overall=14,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=8,overall=20,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            alt=9,overall=16,losers=1 -- refuse
            0 Costly set: reject++
            alt=12: Bad operand -- refuse
            0 Costly set: reject++
            1 Costly loser: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
          alt=13,overall=611,losers=1,rld_nregs=1
            0 Costly set: reject++
          alt=14,overall=1,losers=0,rld_nregs=0
	 Choosing alt 14 in insn 73:  (0) *v  (1) m {*movdi_internal}
            0 Non input pseudo reload: reject++
            1 Dying matched operand reload: reject++
          alt=0,overall=8,losers=1,rld_nregs=2
            0 Non input pseudo reload: reject++
            1 Dying matched operand reload: reject++
          alt=0,overall=8,losers=1,rld_nregs=2
	 Choosing alt 0 in insn 28:  (0) =x  (1) %0  (2) xm {*iorv2di3}
      Creating newreg=132, assigning class SSE_REGS to r132
   28: r132:V2DI=r132:V2DI|r126:DI#0
      REG_DEAD r126:DI
      REG_DEAD r118:DI
    Inserting insn reload before:
   81: r132:V2DI=r118:DI#0
    Inserting insn reload after:
   82: r108:DI#0=r132:V2DI

            0 Non input pseudo reload: reject++
            alt=0: Bad operand -- refuse
            0 Non input pseudo reload: reject++
            1 Non pseudo reload: reject++
          alt=1,overall=608,losers=1,rld_nregs=1
            0 Non pseudo reload: reject++
            1 Non pseudo reload: reject++
          alt=2,overall=2,losers=0,rld_nregs=0
	 Choosing alt 2 in insn 82:  (0) m  (1) v {*movv2di_internal}
            0 Non pseudo reload: reject++
            alt=0: Bad operand -- refuse
            0 Non pseudo reload: reject++
          alt=1,overall=1,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 81:  (0) v  (1) vm {*movv2di_internal}
            alt=0: Bad operand -- refuse
            1 Non pseudo reload: reject++
          alt=1,overall=1,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 68:  (0) v  (1) vm {*movv2di_internal}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 77:  (0) =r  (1) mYj {*vec_extractv4si_0}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 70:  (0) =x  (1) 0  (2) xN {lshrv2di3}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 78:  (0) =r  (1) mYj {*vec_extractv4si_0}
            0 Scratch win: reject+=2
          alt=0,overall=14,losers=2,rld_nregs=2
            0 Scratch win: reject+=2
          alt=0,overall=14,losers=2,rld_nregs=2
	 Choosing alt 0 in insn 30:  (0) =r  (1) %0  (2) rme {*iorsi_3}
      Creating newreg=133 from oldreg=130, assigning class GENERAL_REGS to r133
      Change to class INDEX_REGS for r130
   30: {flags:CCZ=cmp(r133:SI|r128:SI,0);clobber r133:SI;}
      REG_UNUSED r130:SI
      REG_DEAD r129:SI
      REG_DEAD r128:SI
    Inserting insn reload before:
   83: r133:SI=r129:SI

            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            1 Non pseudo reload: reject++
          alt=0,overall=10,losers=1,rld_nregs=2
          alt=1,overall=6,losers=1,rld_nregs=2
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=6,overall=10,losers=1 -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=7,overall=10,losers=1 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=8,overall=16,losers=1 -- refuse
            Staticly defined alt reject+=6
            1 Costly loser: reject++
            alt=9,overall=13,losers=1 -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=12,overall=10,losers=1 -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=13,overall=10,losers=1 -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=14,overall=10,losers=1 -- refuse
            1 Costly loser: reject++
            alt=15,overall=7,losers=1 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=19,overall=16,losers=1 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=20,overall=16,losers=1 -- refuse
            alt=22: Bad operand -- refuse
            alt=24: Bad operand -- refuse
	 Choosing alt 1 in insn 38:  (0) o  (1) riF {*movdi_internal}
      Creating newreg=134 from oldreg=108, assigning class GENERAL_REGS to r134
   38: [sp:SI]=r134:DI
    Inserting insn reload before:
   84: r134:DI=r108:DI

            0 Non pseudo reload: reject++
            1 Non pseudo reload: reject++
          alt=0,overall=2,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 84:  (0) =r  (1) riFo {*movdi_internal}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 40:  (0) lBwBz {*call}
          alt=0,overall=0,losers=0,rld_nregs=0
            1 Matching alt: reject+=2
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=0,overall=11,losers=1 -- refuse
            1 Matching alt: reject+=2
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=1,overall=11,losers=1 -- refuse
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=2,overall=9,losers=1 -- refuse
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=3,overall=9,losers=1 -- refuse
	 Choosing alt 0 in insn 41:  (0) =r  (1) %0  (2) rme {*addsi_1}
            0 Non input pseudo reload: reject++
          alt=0,overall=13,losers=2,rld_nregs=2
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=1,overall=19,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=6,overall=14,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=7,overall=14,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=8,overall=20,losers=2 -- refuse
            Staticly defined alt reject+=6
            0 Spill pseudo into memory: reject+=3
            0 Non input pseudo reload: reject++
            alt=9,overall=16,losers=1 -- refuse
            0 Costly set: reject++
            alt=12: Bad operand -- refuse
            0 Costly set: reject++
            1 Costly loser: reject++
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
          alt=13,overall=611,losers=1,rld_nregs=1
            0 Costly set: reject++
          alt=14,overall=1,losers=0,rld_nregs=0
	 Choosing alt 14 in insn 74:  (0) *v  (1) m {*movdi_internal}
            0 Non input pseudo reload: reject++
          alt=0,overall=13,losers=2,rld_nregs=2
            0 Non input pseudo reload: reject++
            1 Dying matched operand reload: reject++
            2 Non pseudo reload: reject++
          alt=0,overall=9,losers=1,rld_nregs=2
  Commutative operand exchange in insn 42
	 Choosing alt 0 in insn 42:  (0) =x  (1) %0  (2) xm {*andv2di3}
      Creating newreg=135, assigning class SSE_REGS to r135
   42: r135:V2DI=r135:V2DI&r108:DI#0
      REG_DEAD r127:DI
    Inserting insn reload before:
   85: r135:V2DI=r127:DI#0
    Inserting insn reload after:
   86: r108:DI#0=r135:V2DI

            0 Non input pseudo reload: reject++
            alt=0: Bad operand -- refuse
            0 Non input pseudo reload: reject++
            1 Non pseudo reload: reject++
          alt=1,overall=608,losers=1,rld_nregs=1
            0 Non pseudo reload: reject++
            1 Non pseudo reload: reject++
          alt=2,overall=2,losers=0,rld_nregs=0
	 Choosing alt 2 in insn 86:  (0) m  (1) v {*movv2di_internal}
            0 Non pseudo reload: reject++
            alt=0: Bad operand -- refuse
            0 Non pseudo reload: reject++
          alt=1,overall=1,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 85:  (0) v  (1) vm {*movv2di_internal}
            alt=0: Bad operand -- refuse
            1 Non pseudo reload: reject++
          alt=1,overall=1,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 64:  (0) v  (1) vm {*movv2di_internal}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 75:  (0) =r  (1) mYj {*vec_extractv4si_0}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 66:  (0) =x  (1) 0  (2) xN {lshrv2di3}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 76:  (0) =r  (1) mYj {*vec_extractv4si_0}
            0 Scratch win: reject+=2
          alt=0,overall=14,losers=2,rld_nregs=2
            0 Scratch win: reject+=2
          alt=0,overall=14,losers=2,rld_nregs=2
	 Choosing alt 0 in insn 45:  (0) =r  (1) %0  (2) rme {*iorsi_3}
      Creating newreg=136 from oldreg=131, assigning class GENERAL_REGS to r136
      Change to class INDEX_REGS for r131
   45: {flags:CCZ=cmp(r136:SI|r128:SI,0);clobber r136:SI;}
      REG_UNUSED r131:SI
      REG_DEAD r129:SI
      REG_DEAD r128:SI
    Inserting insn reload before:
   87: r136:SI=r129:SI

	   Spilling non-eliminable hard regs: 7

********** Pseudo live ranges #1: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
	Hard reg 0 is preferable by r136 with profit 910
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 86: point = 8
   Insn 42: point = 10
   Insn 85: point = 11
   Insn 74: point = 13
   Insn 41: point = 14
   Insn 40: point = 14
   Insn 39: point = 14
   Insn 38: point = 14
   Insn 84: point = 15
  BB 2
   Insn 31: point = 17
   Insn 30: point = 17
   Insn 83: point = 19
	Hard reg 0 is preferable by r133 with profit 90
   Insn 78: point = 21
   Insn 70: point = 23
   Insn 77: point = 23
   Insn 68: point = 24
   Insn 82: point = 25
   Insn 28: point = 27
   Insn 81: point = 28
   Insn 73: point = 30
   Insn 27: point = 31
   Insn 72: point = 33
   Insn 26: point = 34
   Insn 22: point = 35
   Insn 79: point = 36
 r107: [0..36]
 r108: [10..25] [0..8]
 r117: [0..35]
 r118: [29..31]
 r119: [32..34]
 r123: [5..7]
 r124: [22..24]
 r125: [32..33]
 r126: [27..30]
 r127: [12..13]
 r128: [18..23] [1..6]
 r129: [20..21] [3..4]
 r132: [26..28]
 r133: [17..19]
 r134: [14..15]
 r135: [9..11]
 r136: [0..2]
Compressing live ranges: from 37 to 24 - 64%
Ranges after the compression:
 r107: [0..23]
 r108: [0..17]
 r117: [0..23]
 r118: [20..21]
 r119: [22..23]
 r123: [4..5]
 r124: [16..17]
 r125: [22..23]
 r126: [18..21]
 r127: [8..9]
 r128: [12..17] [0..5]
 r129: [14..15] [2..3]
 r132: [18..19]
 r133: [12..13]
 r134: [10..11]
 r135: [6..7]
 r136: [0..1]

********** Inheritance #1: **********

EBB 2
    <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      Creating newreg=137 from oldreg=108, assigning class NO_REX_SSE_REGS to inheritance r137
    Original reg change 108->137 (bb2):
   82: r137:DI#0=r132:V2DI
      REG_DEAD r132:V2DI
    Add original<-inheritance after:
   88: r108:DI=r137:DI

    Inheritance reuse change 108->137 (bb2):
   68: r124:V2DI=r137:DI#0
	  >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
EBB 3
    <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      Creating newreg=138 from oldreg=108, assigning class NO_REX_SSE_REGS to inheritance r138
    Original reg change 108->138 (bb3):
   86: r137:DI#0=r135:V2DI
      REG_DEAD r135:V2DI
    Add original<-inheritance after:
   89: r108:DI=r138:DI

    Inheritance reuse change 108->138 (bb3):
   64: r123:V2DI=r137:DI#0
	  >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
    <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
    Rejecting inheritance for 108 because of disjoint classes GENERAL_REGS and NO_REX_SSE_REGS
    >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
EBB 4

********** Pseudo live ranges #2: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
	Hard reg 0 is preferable by r136 with profit 910
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 89: point = 9
   Insn 86: point = 11
   Insn 42: point = 13
   Insn 85: point = 14
   Insn 74: point = 16
   Insn 41: point = 17
   Insn 40: point = 17
   Insn 39: point = 17
   Insn 38: point = 17
   Insn 84: point = 18
  r138 is added to live at bb3 start
  BB 2
   Insn 31: point = 20
   Insn 30: point = 20
   Insn 83: point = 22
	Hard reg 0 is preferable by r133 with profit 90
   Insn 78: point = 24
   Insn 70: point = 26
   Insn 77: point = 26
   Insn 68: point = 27
   Insn 88: point = 29
   Insn 82: point = 30
   Insn 28: point = 32
   Insn 81: point = 33
   Insn 73: point = 35
   Insn 27: point = 36
   Insn 72: point = 38
   Insn 26: point = 39
   Insn 22: point = 40
   Insn 79: point = 41
Global pseudo live data have been updated:

BB 2:
    killed: 2:

      107  108  117  118  119  124  125  126  128  129  132
      133  137
    livein: 2:

      138
    liveout: 2:

        6    7   16   20  107  108  117  138

BB 3:
    gen: 3:

      107  108  117  138
    killed: 3:

      108  123  127  128  129  134  135  136  137
    livein: 3:

      107  108  117  138
    liveout: 3:

        6    7   16   20  107  108  117  138

BB 4:
    liveout: 4:

        6    7   16   20
 r107: [0..41]
 r108: [13..29] [0..9]
 r117: [0..40]
 r118: [34..36]
 r119: [37..39]
 r123: [5..7]
 r124: [25..27]
 r125: [37..38]
 r126: [32..35]
 r127: [15..16]
 r128: [21..26] [1..6]
 r129: [23..24] [3..4]
 r132: [31..33]
 r133: [20..22]
 r134: [17..18]
 r135: [12..14]
 r136: [0..2]
 r137: [28..30] [8..11]
 r138: [10..19]
Compressing live ranges: from 42 to 30 - 71%
Ranges after the compression:
 r107: [0..29]
 r108: [10..23] [0..7]
 r117: [0..29]
 r118: [26..27]
 r119: [28..29]
 r123: [4..5]
 r124: [20..21]
 r125: [28..29]
 r126: [24..27]
 r127: [12..13]
 r128: [16..21] [0..5]
 r129: [18..19] [2..3]
 r132: [24..25]
 r133: [16..17]
 r134: [14..15]
 r135: [10..11]
 r136: [0..1]
 r137: [22..23] [6..9]
 r138: [8..15]
Live info was changed -- recalculate it

********** Pseudo live ranges #3: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
	Hard reg 0 is preferable by r136 with profit 910
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 89: point = 9
   Insn 86: point = 10
   Insn 42: point = 12
   Insn 85: point = 13
   Insn 74: point = 15
   Insn 41: point = 16
   Insn 40: point = 16
   Insn 39: point = 16
   Insn 38: point = 16
   Insn 84: point = 17
  BB 2
   Insn 31: point = 19
   Insn 30: point = 19
   Insn 83: point = 21
	Hard reg 0 is preferable by r133 with profit 90
   Insn 78: point = 23
   Insn 70: point = 25
   Insn 77: point = 25
   Insn 68: point = 26
   Insn 88: point = 28
   Insn 82: point = 29
   Insn 28: point = 31
   Insn 81: point = 32
   Insn 73: point = 34
   Insn 27: point = 35
   Insn 72: point = 37
   Insn 26: point = 38
   Insn 22: point = 39
   Insn 79: point = 40
 r107: [0..40]
 r108: [12..28] [0..9]
 r117: [0..39]
 r118: [33..35]
 r119: [36..38]
 r123: [5..7]
 r124: [24..26]
 r125: [36..37]
 r126: [31..34]
 r127: [14..15]
 r128: [20..25] [1..6]
 r129: [22..23] [3..4]
 r132: [30..32]
 r133: [19..21]
 r134: [16..17]
 r135: [11..13]
 r136: [0..2]
 r137: [27..29] [8..10]
 r138: [0..41]
Compressing live ranges: from 42 to 28 - 66%
Ranges after the compression:
 r107: [0..27]
 r108: [0..21]
 r117: [0..27]
 r118: [24..25]
 r119: [26..27]
 r123: [4..5]
 r124: [18..19]
 r125: [26..27]
 r126: [22..25]
 r127: [10..11]
 r128: [14..19] [0..5]
 r129: [16..17] [2..3]
 r132: [22..23]
 r133: [14..15]
 r134: [12..13]
 r135: [8..9]
 r136: [0..1]
 r137: [20..21] [6..7]
 r138: [0..27]

********** Assignment #1: **********

	 Assigning to 134 (cl=GENERAL_REGS, orig=108, freq=1820, tfirst=134, tfreq=1820)...
	   Assign 0 to reload r134 (freq=1820)
	 Assigning to 136 (cl=GENERAL_REGS, orig=131, freq=1820, tfirst=136, tfreq=1820)...
	   Assign 0 to reload r136 (freq=1820)
	 Assigning to 133 (cl=GENERAL_REGS, orig=130, freq=180, tfirst=133, tfreq=180)...
	   Assign 0 to reload r133 (freq=180)
	 Assigning to 135 (cl=SSE_REGS, orig=135, freq=2730, tfirst=135, tfreq=2730)...
	   Assign 23 to reload r135 (freq=2730)
	 Assigning to 137 (cl=NO_REX_SSE_REGS, orig=108, freq=2090, tfirst=137, tfreq=2090)...
	   Assign 24 to inheritance r137 (freq=2090)
	 Assigning to 138 (cl=NO_REX_SSE_REGS, orig=108, freq=910, tfirst=138, tfreq=910)...
	 Assigning to 132 (cl=SSE_REGS, orig=132, freq=270, tfirst=132, tfreq=270)...
	   Assign 25 to reload r132 (freq=270)
  Reassigning non-reload pseudos

********** Undoing inheritance #1: **********

Inherit 1 out of 2 (50.00%)
	   Removing inheritance:
   89: r108:DI=r138:DI

********** Local #2: **********

	   Spilling non-eliminable hard regs: 7
            alt=0: Bad operand -- refuse
          alt=1,overall=0,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 86:  (0) v  (1) vm {*movv2di_internal}
            alt=0: Bad operand -- refuse
          alt=1,overall=0,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 82:  (0) v  (1) vm {*movv2di_internal}
            alt=0: Bad operand -- refuse
          alt=1,overall=0,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 68:  (0) v  (1) vm {*movv2di_internal}
            alt=0: Bad operand -- refuse
          alt=1,overall=0,losers=0,rld_nregs=0
	 Choosing alt 1 in insn 64:  (0) v  (1) vm {*movv2di_internal}
            0 Non input pseudo reload: reject++
          alt=0,overall=19,losers=3,rld_nregs=4
            0 Non pseudo reload: reject++
          alt=1,overall=13,losers=2,rld_nregs=2
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=6: Bad operand -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            1 Costly loser: reject++
            alt=7,overall=21,losers=3 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=8,overall=14,losers=1 -- refuse
            Staticly defined alt reject+=6
            0 Non pseudo reload: reject++
            1 Costly loser: reject++
            alt=9,overall=20,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            alt=12: Bad operand -- refuse
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            1 Costly set: reject++
          alt=13,overall=609,losers=1,rld_nregs=1
            0 Costly loser: reject++
            0 Non input pseudo reload: reject++
            1 Spill pseudo into memory: reject+=3
            alt=14,overall=17,losers=2 -- refuse
            0 Non pseudo reload: reject++
            1 Costly set: reject++
          alt=15,overall=2,losers=0,rld_nregs=0
	 Choosing alt 15 in insn 88:  (0) m  (1) *v {*movdi_internal}

********** Pseudo live ranges #4: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 86: point = 9
   Insn 42: point = 11
   Insn 85: point = 11
   Insn 74: point = 13
   Insn 41: point = 14
   Insn 40: point = 14
   Insn 39: point = 14
   Insn 38: point = 14
   Insn 84: point = 15
  BB 2
   Insn 31: point = 17
   Insn 30: point = 17
   Insn 83: point = 19
   Insn 78: point = 21
   Insn 70: point = 23
   Insn 77: point = 23
   Insn 68: point = 24
   Insn 88: point = 26
   Insn 82: point = 27
   Insn 28: point = 29
   Insn 81: point = 30
   Insn 73: point = 32
   Insn 27: point = 33
   Insn 72: point = 35
   Insn 26: point = 36
   Insn 22: point = 37
   Insn 79: point = 38
  r108 is removed as live at bb2 start
Global pseudo live data have been updated:

BB 2:
    killed: 2:

      107  108  117  118  119  124  125  126  128  129  132
      133  137
    liveout: 2:

        6    7   16   20  107  108  117

BB 3:
    gen: 3:

      107  108  117
    killed: 3:

      123  127  128  129  134  135  136  137
    livein: 3:

      107  108  117
    liveout: 3:

        6    7   16   20  107  108  117

BB 4:
    liveout: 4:

        6    7   16   20
 r108: [0..26]
Compressing live ranges: from 39 to 2 - 5%
Ranges after the compression:
 r108: [0..1]
Live info was changed -- recalculate it

********** Pseudo live ranges #5: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 86: point = 9
   Insn 42: point = 11
   Insn 85: point = 11
   Insn 74: point = 13
   Insn 41: point = 14
   Insn 40: point = 14
   Insn 39: point = 14
   Insn 38: point = 14
   Insn 84: point = 15
  BB 2
   Insn 31: point = 17
   Insn 30: point = 17
   Insn 83: point = 19
   Insn 78: point = 21
   Insn 70: point = 23
   Insn 77: point = 23
   Insn 68: point = 24
   Insn 88: point = 26
   Insn 82: point = 27
   Insn 28: point = 29
   Insn 81: point = 30
   Insn 73: point = 32
   Insn 27: point = 33
   Insn 72: point = 35
   Insn 26: point = 36
   Insn 22: point = 37
   Insn 79: point = 38
 r108: [0..26]
Compressing live ranges: from 39 to 2 - 5%
Ranges after the compression:
 r108: [0..1]

******** Rematerialization #1: ********


Cands:
0 (nop=0, remat_regno=108, reload_regno=-1):
(insn 88 82 68 2 (set (reg/v:DI 108 [ tmp ])
                    (reg/v:DI 137 [orig:108 tmp ] [108])) small.c:9 89 {*movdi_internal}
                 (nil))

BB 2:
  register live in:
  register live out: 6 [bp] 7 [sp] 16 [argp] 20 [frame] 107 108 117
  changed regs: 107 108 117 118 119 124 125 126 128 129 132 133 137
  dead regs: 16 [argp] 17 [flags] 118 119 124 125 126 128 129 132 137

BB 3:
  register live in: 107 108 117
  register live out: 6 [bp] 7 [sp] 16 [argp] 20 [frame] 107 108 117
  changed regs: 3 [bx] 117 123 127 128 129 134 135 136 137
  dead regs: 0 [ax] 1 [dx] 2 [cx] 7 [sp] 8 [st] 9 [st(1)] 10 [st(2)] 11 [st(3)] 12 [st(4)] 13 [st(5)] 14 [st(6)] 15 [st(7)] 16 [argp] 17 [flags] 18 [fpsr] 19 [fpcr] 20 [frame] 21 [xmm0] 22 [xmm1] 23 [xmm2] 24 [xmm3] 25 [xmm4] 26 [xmm5] 27 [xmm6] 28 [xmm7] 29 [mm0] 30 [mm1] 31 [mm2] 32 [mm3] 33 [mm4] 34 [mm5] 35 [mm6] 36 [mm7] 37 [] 38 [] 39 [] 40 [] 41 [] 42 [] 43 [] 44 [] 45 [] 46 [] 47 [] 48 [] 49 [] 50 [] 51 [] 52 [] 53 [] 54 [] 55 [] 56 [] 57 [] 58 [] 59 [] 60 [] 61 [] 62 [] 63 [] 64 [] 65 [] 66 [] 67 [] 68 [] 69 [] 70 [] 71 [] 72 [] 73 [] 74 [] 75 [] 76 [] 77 [] 78 [] 79 [] 80 [] 123 127 128 129 134 135 137

BB 4:
  register live in:
  register live out: 6 [bp] 7 [sp] 16 [argp] 20 [frame]
  changed regs:
  dead regs:
  Slot 0 regnos (width = 8):	 108
Changing spilled pseudos to memory in insn #88
Changing spilled pseudos to memory in insn #84
Changing spilled pseudos to memory in insn #42
	   Spilling non-eliminable hard regs: 7
New elimination table:
Can eliminate 16 to 7 (offset=48, prev_offset=32)
Can eliminate 16 to 6 (offset=4, prev_offset=0)
Can eliminate 20 to 7 (offset=32, prev_offset=16)
Can eliminate 20 to 6 (offset=-12, prev_offset=0)

********** Local #3: **********

	   Spilling non-eliminable hard regs: 7
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 22:  (0) =r  (1) g {*movsi_internal}
          alt=0,overall=0,losers=0,rld_nregs=0
            1 Matching alt: reject+=2
            1 Non-pseudo reload: reject+=2
            1 Non input pseudo reload: reject++
            alt=0,overall=11,losers=1 -- refuse
	 Choosing alt 0 in insn 42:  (0) =x  (1) %0  (2) xm {*andv2di3}
          alt=0,overall=0,losers=0,rld_nregs=0
	 Choosing alt 0 in insn 84:  (0) =r  (1) riFo {*movdi_internal}
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
          alt=0,overall=21,losers=3,rld_nregs=4
          alt=1,overall=12,losers=2,rld_nregs=2
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=6: Bad operand -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            1 Costly loser: reject++
            alt=7,overall=23,losers=3 -- refuse
            Staticly defined alt reject+=6
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=8,overall=16,losers=1 -- refuse
            Staticly defined alt reject+=6
            1 Costly loser: reject++
            alt=9,overall=19,losers=2 -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            alt=12: Bad operand -- refuse
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            1 Costly set: reject++
          alt=13,overall=611,losers=1,rld_nregs=1
            0 Costly loser: reject++
            0 Non-pseudo reload: reject+=2
            0 Non input pseudo reload: reject++
            1 Spill pseudo into memory: reject+=3
            alt=14,overall=19,losers=2 -- refuse
            1 Costly set: reject++
          alt=15,overall=1,losers=0,rld_nregs=0
	 Choosing alt 15 in insn 88:  (0) m  (1) *v {*movdi_internal}
	   Spilling non-eliminable hard regs: 7

********** Pseudo live ranges #6: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 86: point = 9
   Insn 42: point = 11
   Insn 85: point = 11
   Insn 74: point = 13
   Insn 41: point = 14
   Insn 40: point = 14
   Insn 39: point = 14
   Insn 38: point = 14
   Insn 84: point = 15
  BB 2
   Insn 31: point = 17
   Insn 30: point = 17
   Insn 83: point = 19
   Insn 78: point = 21
   Insn 70: point = 23
   Insn 77: point = 23
   Insn 68: point = 24
   Insn 88: point = 26
   Insn 82: point = 26
   Insn 28: point = 28
   Insn 81: point = 29
   Insn 73: point = 31
   Insn 27: point = 32
   Insn 72: point = 34
   Insn 26: point = 35
   Insn 22: point = 36
   Insn 79: point = 37
 r107: [0..37]
 r117: [0..36]
 r118: [30..32]
 r119: [33..35]
 r123: [5..7]
 r124: [22..24]
 r125: [33..34]
 r126: [28..31]
 r127: [12..13]
 r128: [18..23] [1..6]
 r129: [20..21] [3..4]
 r132: [27..29]
 r133: [17..19]
 r134: [14..15]
 r135: [10..11]
 r136: [0..2]
 r137: [25..26] [8..9]
Compressing live ranges: from 38 to 28 - 73%
Ranges after the compression:
 r107: [0..27]
 r117: [0..27]
 r118: [24..25]
 r119: [26..27]
 r123: [4..5]
 r124: [18..19]
 r125: [26..27]
 r126: [22..25]
 r127: [10..11]
 r128: [14..19] [0..5]
 r129: [16..17] [2..3]
 r132: [22..23]
 r133: [14..15]
 r134: [12..13]
 r135: [8..9]
 r136: [0..1]
 r137: [20..21] [6..7]

********** Inheritance #2: **********

EBB 2
EBB 3
EBB 4

********** Pseudo live ranges #7: **********

  BB 4
  BB 3
   Insn 46: point = 0
   Insn 45: point = 0
   Insn 87: point = 2
   Insn 76: point = 4
   Insn 66: point = 6
   Insn 75: point = 6
   Insn 64: point = 7
   Insn 86: point = 9
   Insn 42: point = 11
   Insn 85: point = 11
   Insn 74: point = 13
   Insn 41: point = 14
   Insn 40: point = 14
   Insn 39: point = 14
   Insn 38: point = 14
   Insn 84: point = 15
  BB 2
   Insn 31: point = 17
   Insn 30: point = 17
   Insn 83: point = 19
   Insn 78: point = 21
   Insn 70: point = 23
   Insn 77: point = 23
   Insn 68: point = 24
   Insn 88: point = 26
   Insn 82: point = 26
   Insn 28: point = 28
   Insn 81: point = 29
   Insn 73: point = 31
   Insn 27: point = 32
   Insn 72: point = 34
   Insn 26: point = 35
   Insn 22: point = 36
   Insn 79: point = 37
 r107: [0..37]
 r117: [0..36]
 r118: [30..32]
 r119: [33..35]
 r123: [5..7]
 r124: [22..24]
 r125: [33..34]
 r126: [28..31]
 r127: [12..13]
 r128: [18..23] [1..6]
 r129: [20..21] [3..4]
 r132: [27..29]
 r133: [17..19]
 r134: [14..15]
 r135: [10..11]
 r136: [0..2]
 r137: [25..26] [8..9]
Compressing live ranges: from 38 to 28 - 73%
Ranges after the compression:
 r107: [0..27]
 r117: [0..27]
 r118: [24..25]
 r119: [26..27]
 r123: [4..5]
 r124: [18..19]
 r125: [26..27]
 r126: [22..25]
 r127: [10..11]
 r128: [14..19] [0..5]
 r129: [16..17] [2..3]
 r132: [22..23]
 r133: [14..15]
 r134: [12..13]
 r135: [8..9]
 r136: [0..1]
 r137: [20..21] [6..7]

********** Assignment #2: **********


********** Undoing inheritance #2: **********


********** Local #4: **********

	   Spilling non-eliminable hard regs: 7
	   Spilling non-eliminable hard regs: 7
New elimination table:
Can eliminate 16 to 7 (offset=48, prev_offset=48)
Can eliminate 16 to 6 (offset=4, prev_offset=0)
Can eliminate 20 to 7 (offset=32, prev_offset=32)
Can eliminate 20 to 6 (offset=-12, prev_offset=0)


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