match_scratch causing pattern mismatch

[Paul Shortis]

in a GCC port to a 16 bit cpu that uses CC flags for branching, 
I'm experimenting with using a 32 bit subtract for compare 
instead of multiple 16 bit compares and branches.

my cbranch<mode>4 expander produces a compare and conditional 
branch patterns...

   cmpmode = SELECT_CC_MODE( branchCode, op0, op1 );
   flags = gen_rtx_REG ( cmpmode, CC_REGNUM );

   compare = gen_rtx_COMPARE ( cmpmode, op0, op1 );
   emit_insn( gen_rtx_SET( VOIDmode, flags, compare ));

To implement compare using a subtract I need a HI mode scratch 
register, so I used a match_scratch

(define_insn "comparesi3"
   [ (set (reg:CC CC_REGNUM)
             (compare:CC (match_operand:SI 0 "register_operand" 
"r,r")
                                   (match_operand:SI 1 
"rhs_operand" "r,i")))
    (clobber(match_scratch:HI 2 "=r,r"))
   ]
   ""


When I do this, the compare no longer matches and I get failures 
like this in the vregs pass...

../../../libgcc/unwind-dw2.c:1224:1: error: unrecognizable insn:
  }
  ^
(insn 69 68 70 7 (set (reg:CC 16 flags)
         (compare:CC (reg:SI 44 [ D.5851 ])
             (reg:SI 169))) ../../../libgcc/unwind-dw2.c:972 -1
      (nil))

when I remove the match_scratch these errors disappear, but of 
course I don't have the scratch register needed to implement the 
proper assembler instructions

I'm aware that it's the combiner that understands clobbers etc.  
So, in the .md file I tried to add a dummy comparesi3 pattern 
that doesn't have the match_scratch... after the pattern 
containing the match_scratch. This sometimes works, however on 
occasion the dummy pattern is selected by the combiner instead of 
the match_scratch pattern .

Any insight appreciated...

Cheers, Paul