Possible issue with ARC gcc 4.8

[Vineet Gupta]

On Monday 06 July 2015 12:04 PM, Richard Biener wrote:
>> The point being ARC ISA provides a neat feature where core only considers lower 5
>> > bits of bitpos operands. Thus we can make such behaviour not only deterministic in
>> > the context of ARC, but also optimal, eliding the need for doing specific
>> > masking/clamping to 5 bits.
> There is SHIFT_COUNT_TRUNCATED which allows you to combine
> b & 31 with the shift value if you instead write a << (b & 31).

Awesome, this is what we need for ARC then along with the user code change to add
the masking so the combiner will nullify the masking.

>
> Of course a << 63 is still undefined behavior regardless of target behavior.

Sure

Thx,
-Vineet