LRA handling of subreg (on AARCH64 with ILP32)

[Ramana Radhakrishnan]

On Thu, Jan 15, 2015 at 4:11 AM, Andrew Pinski <pinskia@gmail.com> wrote:
> Hi,
>   I have some code where we generate some weird code that has stores
> followed by a load from the same location.
> For an example we get:
> add x14, sp, 240
> add x15, sp, 232
> str x14, [sp, 136]
> mov w2, w27
> ldr w1, [sp, 136]
> str x15, [sp, 136]
> ldr w0, [sp, 136]
>
> The RTL originally using an offset of the frame pointer and in DImode
> and then we use it in SImode because pointers are 32bit in ILP32.
> Can you explain how LRA decides to create this code and ways of improving it?
>
> This is in perlbench in SPEC CPU 2006. I can provide the preprocessed
> sources (since I am using LTO) if needed.

I wonder if this is similar to

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55769

on ARM.


I thought I'd seen this before - this is a case where A, B and C
appear to store a 64 bit value on the stack and then reobtain into a
different register set , ie. r6, r3 -> r6, r7

Ramana

>
> Thanks,
> Andrew Pinski