Support for architectures without hardware interlocks

[Eric Botcazou]

> Handling the insertion of the nops at the end of RTL pipe needs to
> take also care of branch shortening optimizations, and filling delay
> slots. Probably for the given context (only FPU ops) may be a doable
> approach.

Right, you do it after delay slot filling and before branch shortening.
The new Visium port does that for all instructions (see visium_reorg).

-- 
Eric Botcazou