Instruction scheduler with respect to prefetch instructions.

[Ajit Kumar Agarwal]

-----Original Message-----
From: Paul_Koning@Dell.com [mailto:Paul_Koning@Dell.com] 
Sent: Saturday, December 13, 2014 9:46 PM
To: Ajit Kumar Agarwal
Cc: vmakarov@redhat.com; law@redhat.com; richard.guenther@gmail.com; gcc@gcc.gnu.org; Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: Re: Instruction scheduler with respect to prefetch instructions.


> On Dec 13, 2014, at 5:22 AM, Ajit Kumar Agarwal <ajit.kumar.agarwal@xilinx.com> wrote:
> 
> Hello All:
> 
> Since the prefetch instruction have no direct consumers  in the code 
> stream, they provide considerable freedom to the Instruction scheduler. They are typically assigned lower priorities than most of the instructions in the code stream.
> This tends to cause all the prefetch instructions to be placed 
> together in the final schedule. This causes the performance Degradations by placing them in clumps rather than evenly spreading the prefetch instructions.
> 
> The evenly spreading the prefetch instruction gives better speed up 
> ratios as compared to be placing in clumps for dirty Misses.

>>I can believe that’s true for some processors; is it true for all of them?  I have the impression that some MIPS processors don’t mind clumped prefetches, >>so long as you don’t exceed the limit on total number of concurrently pending memory accesses.

I think it's okay to have clumped prefetches for architectures  that are decided based on prefetch distance as long
it doesn't exceed the concurrent pending memory access. The clumped prefetches that are generated by the 
scheduler as there are no direct consumers in the code stream sometimes exceed the concurrent pending memory
access if the special mechanism is not done by the scheduler like some information to be passed from the generation
of prefetch algorithm phase to the scheduler.

Due to the freedom provided to instruction scheduler for not having direct consumers in the code stream, clumps
the prefetch instructions at the end of the basic blocks which will  invalidates the actual place where the prefetch
instruction is generated based on the prefetch distance.

The prefetch algorithms based on prefetch distance takes care of the cases where the clumped prefetches degraded
the performance due to dirty misses.

My question is there any special way of handling the prefetch instruction with respect to the instruction scheduler to
overcome the above.
 
Thanks & Regards
Ajit

	paul