Identical basic blocks live long in RTL flow.

[Jeff Law]

On 01/17/13 03:39, Bin.Cheng wrote:
> On Thu, Jan 17, 2013 at 1:29 AM, Jan Hubicka <hubicka@ucw.cz> wrote:
>>>>
>>>> Basic blocks 8/9/10 are identical and live until pass jump2, which is
>>>> after register allocation.
>>>> I think these duplicated BBs do not contain additional information and
>>>> should be better to be removed ASAP, because they might interfere with
>>>> other passes like ifcvt.
>>>>
>>>> So should this issue be handled like in jump pass?
>>> In this case, I'd expect DCE to optimize away the redundant assignments.
>>
>> Yeah, we also used to be able to optimize these out in crossjumping before
>> regalloc but with SSA we now produce different pseudos in different copies so I
>> think it was path by Steven that disabled crossjumping proir jump2 (both passes
>> also ought to be renamed)
>>
>
> Unfortunately, this case can't be handled by DCE because just before
> pass pass_into_cfg_layout_mode, the rtl is like:
>
>
>      1: NOTE_INSN_DELETED
>      9: NOTE_INSN_BASIC_BLOCK 2
>      2: r113:SI=r0:SI
>      3: r114:SI=r1:SI
>      4: NOTE_INSN_FUNCTION_BEG
>     11: pc={(r113:SI==0)?L39:pc}
>        REG_BR_PROB 0x3f6
>     12: NOTE_INSN_BASIC_BLOCK 4
>     13: r111:SI=zero_extend([r113:SI])
>     14: pc={(r111:SI==0x2d)?L43:pc}
>        REG_BR_PROB 0x7c7
>     15: NOTE_INSN_BASIC_BLOCK 5
>     16: pc={(r114:SI!=0)?L20:pc}
>        REG_BR_PROB 0x1388
>     22: L22:
>     17: NOTE_INSN_BASIC_BLOCK 6
>      6: r110:SI=0
>     18: pc=L24
>     19: barrier
>     20: L20:
>     21: NOTE_INSN_BASIC_BLOCK 7
>     23: pc={(r111:SI!=0x2b)?L22:pc}
>        REG_BR_PROB 0x1f49
>     35: NOTE_INSN_BASIC_BLOCK 8
>      8: r110:SI=0x1
>     36: pc=L24
>     37: barrier
>     39: L39:
>     38: NOTE_INSN_BASIC_BLOCK 9
>      7: r110:SI=0x1
>     40: pc=L24
>     41: barrier
>     43: L43:
>     42: NOTE_INSN_BASIC_BLOCK 10
>      5: r110:SI=0x1
>     24: L24:
>     25: NOTE_INSN_BASIC_BLOCK 11
>     26: r112:SI=r110:SI
>     30: r0:SI=r112:SI
>     33: use r0:SI
>
> Insns 36/40 is deleted in pass pass_into_cfg_layout_mode to make each
> edge possibly fall-through. The edges <8, 11> and <9, 11> still exist
> in control flow and insns 7/8 are not dead code. It's just coincident
> to have three identical basic blocks here. I don't think any passes
> other than cross-jumping can handle this, right?
Right.  This has to be caught by tail merging/cross jumping which occurs 
during jump2.

jeff