Modeling predicate registers with more than one bit

[Paulo Matos]

Hello,

I am looking at how to correctly model in GCC predicate registers that have more than one bit and the value set into to the predicate register after a comparison depends on the size of the comparison.

I have looked into GCC backends but haven't really found any backend with a similar constraint. Have I missed a backend that has similar requirements? If not, is there any way to currently (as of HEAD) model this in GCC?

Thanks,

Paulo Matos