Porting new target architecture to GCC

[Ben Morgan]

Hello,

In a course at my university (Universität Würzburg, Germany) we have
created a 32-bit RISC CPU architecture -- the HaDesXI-CPU -- (in VHDL)
which we then play onto a FPGA (the Xilinx Spartan-3AN) to use. So far
if we want to do anything with it, we have to write the assembly code
ourselves.

How much work would it be to write a HadesXI backend for GCC?
(The idea is to use this as a possible bachelor thesis.)

Where would be a good place to start; what are the prerequisites for
undertaking a project like this other than knowing the CPU architecture
inside out?

Thanks for your advice,
Ben Morgan