Expanding instructions with condition codes inter-deps

[Paul_Koning@Dell.com]

>From: gcc-owner@gcc.gnu.org [mailto:gcc-owner@gcc.gnu.org] On Behalf Of Richard Henderson
>On 10/17/2011 03:50 AM, Paulo J. Matos wrote:
>>...
>> (for example, it would be ok to output negqi2, xorqi3 and 
>> addc_internal since xorqi3 only sets N and Z, not the Carry bit)
>
>For that you'd have to model all of the flags bits independently.
>I don't believe any target has found that level of complexity to be worth the trouble.

Something like that shows up in the pdp11, where "mov" does not touch C.  And C matters for multi-word arithmetic, and also for unsigned compares.  So I think a CCmode implementation there would  model C separately from the other three flag bits.  So not 4 separate elements but two.  Right now it's a cc0 target but I figure on changing that at some point.  The reasons Paulo mentioned are one of the main reasons for that.

	paul