Instruction scheduler question

[Bernd Schmidt]

On 10/07/11 09:50, BELBACHIR Selim wrote:
> (asm result)
> 
> load d($C2),$R1     <--1st operand for comparison     ctrl,readmem,nothing
> loadi 0,$C4         <- 2nd operand for comparison     ctrl,nothing
> load d($C2+4),$R2   <--no data dependancies           ctrl,readmem,nothing
> cmp $C4,$R1                                           (gsr+ctrl),gsr*2
> nop
> nop
> jmpifeq .L5                                           (ctrl+gsr)            
> 
> (.sched2)
> ;;       20-->    81 $C4=0x0                           :ctrl,nothing
> ;;              dependencies resolved: insn 22
> ;;              Ready-->Q: insn 22: queued for 2 cycles.
> ;;              tick updated: insn 22 into queue with cost=2

Insn 22 is the compare, and the compiler thinks that its operand $C4
becomes available only after two cycles. Presumably the first load to
$R1 has a delay of 3 cycles. So the scheduler places the compare at the
point where its operands are ready. The load to $R2 occurs before it
because it can execute earlier.

If the delays are modeled correctly, I think there's no way to get the
code to run faster.


Bernd