Question about Machine Description

[yazdanbakhsh]

Hi,

As I told I want to add  "ble" intruction in MIPS that works like "beq".

I used from the available branch_equality instruction that shows in the
following paragraph:

--------------------------------------------------------------------------------------------------
(define_insn "branch_equality"
  [(set (pc)
	(if_then_else (match_operator:SI 0 "equality_op"
					 [(match_operand:SI 1 "register_operand" "d")
					  (match_operand:SI 2 "register_operand" "d")])
	(match_operand 3 "pc_or_label_operand" "")
	(match_operand 4 "pc_or_label_operand" "")))]
  ""
  "*
{
  ss_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
  return (operands[3] != pc_rtx)
	? \"%*b%C0%?\\t%z1,%z2,%3\"
	: \"%*b%N0%?\\t%z1,%z2,%4\";
}"
  [(set_attr "type"	"branch")
   (set_attr "mode"	"none")
   (set_attr "length"	"1")])
--------------------------------------------------------------------------------------------------
To add "ble" I changed "equality_op" in the header file to have "ble" as a
acceptable operation.but it didn't work. Do u have any idea? I also saw some
functions in the assembler that handle branchs. Should i changed assembler
for this purpose?

Best Regards



yazdanbakhsh wrote:
> 
> I have read all the documents, and changed some lines but nothing happened
> :(
> 
> Ian Lance Taylor-3 wrote:
>> 
>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>> 
>>> I want to change instruction blez to ble. ble compare two registers and
>>> jump
>>> to the target address if the condition is true.
>> 
>> Read the internals manual to understand how operand predicates and
>> constraints work.  See the hundreds of existing examples.  Ask if you
>> have specific questions.
>> 
>> Ian
>> 
>>> Ian Lance Taylor-3 wrote:
>>>> 
>>>> yazdanbakhsh <amir.yazdanbakhsh@gmail.com> writes:
>>>> 
>>>>> Please assume I'm working with the MIPS. There is a little difference
>>>>> between the MIPS and what I'm actually working on it. How can I remove
>>>>> immediate logical shift right/left from the compiler?
>>>>> I mean If I want the programmer writes an immediate shift, It is
>>>>> compiled
>>>>> to
>>>>> the two instructions:
>>>>>
>>>>> sll %2,%2,5
>>>>>
>>>>> changed to:
>>>>>
>>>>> addi %3,%0,5
>>>>> sllv %2,%2,%3
>>>> 
>>>> Find the insn which generates sll.  Change the operand constraints and
>>>> predicates to reject an immediate operand.
>>>> 
>>>> E.g., in mips.md this is:
>>>> 
>>>> (define_insn "*<optab><mode>3"
>>>>   [(set (match_operand:GPR 0 "register_operand" "=d")
>>>> 	(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>> 		       (match_operand:SI 2 "arith_operand" "dI")))]
>>>>   "!TARGET_MIPS16"
>>>> {
>>>>   if (CONST_INT_P (operands[2]))
>>>>     operands[2] = GEN_INT (INTVAL (operands[2])
>>>> 			   & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>>>> 
>>>>   return "<d><insn>\t%0,%1,%2";
>>>> }
>>>>   [(set_attr "type" "shift")
>>>>    (set_attr "mode" "<MODE>")])
>>>> 
>>>> 
>>>> For operand 2, change the predicate to register_operand and remove the
>>>> 'I' constraint.
>>>> 
>>>> Ian
>>>> 
>>>> 
>>>
>>> -- 
>>> View this message in context:
>>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
>>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>> 
>> 
> 
> 

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