Illegal schedule

[Alex Turjan]

>  Do I have to reorganize the code prior to slot filling? Do
> I have to make sure that some problematic instructions do
> not appear in slots?

Perhaps a easy way to solve the problem would be to claim for branches a memory port a number of stages before and after the IF; to avoid in this way hazards in the delay slots.
Alternatively you can adjust the gcc delay slot filler (reorg.c) for your architecture.