Why is debug_insn built into DDG?

[Bingfeng Mei]

Hello,
I started to look at VTA recently and check whether our port passes
the -fcompare-debug test. Our port contains some extra passes for 
our VLIW target. 

What I have trouble is with our modulo scheduling pass (based on 
IMS algorithm). I noticed that debug_insns are built into DDG, 
and has ANTI-dependence edge drawn between other instruction and them.
This dependencies will affect calculation of ASAP, ALAP etc, therefore
affect ordering algorithm and final scheduling results. Why these
debug_insns are needed in the DDG in the first place? They are skipped
during scheduling anyway. Isn't it waste of compilation time? 

Thanks,
Bingfeng